Van Le

US Patent:

20210375830, Dec 2, 2021

Filed:

Aug 11, 2021

Appl. No.:

17/399185

Inventors:

- Santa Clara CA, US
Johanna Swan - Scottsdale AZ, US
Shawna Liff - Scottsdale AZ, US
Patrick Morrow - Portland OR, US
Gerald Pasdast - San Jose CA, US
Van Le - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 25/065
H01L 23/538
H01L 23/522
H01L 23/00
H01L 25/00

Abstract:

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

US Patent:

20210098422, Apr 1, 2021

Filed:

Sep 27, 2019

Appl. No.:

16/586145

Inventors:

- Santa Clara CA, US
Johanna Swan - Scottsdale AZ, US
Shawna Liff - Scottsdale AZ, US
Patrick Morrow - Portland OR, US
Gerald Pasdast - San Jose CA, US
Van Le - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 25/065
H01L 23/538
H01L 23/522
H01L 23/00
H01L 25/00

Abstract:

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.