Victor O Levchenko

US Patent:

60727209, Jun 6, 2000

Filed:

Dec 4, 1998

Appl. No.:

9/205876

Inventors:

Jack Zezhong Peng - San Jose CA
Robert M. Salter - Saratoga CA
Volker Hecht - Los Altos CA
Kyung Joon Han - Cupertino CA
Robert U. Broze - Santa Cruz CA
Victor Levchenko - San Francisco CA

Assignee:

GateField Corporation - Fremont CA

International Classification:

G11C 1604

US Classification:

36518505

Abstract:

Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.

US Patent:

58380400, Nov 17, 1998

Filed:

Mar 31, 1997

Appl. No.:

8/829374

Inventors:

Robert M. Salter - Saratoga CA
Kyung Joon Han - Cupertino CA
Jack Zezhong Peng - San Jose CA
Victor Levchenko - San Francisco CA
Robert V. Broze - Santa Cruz CA

Assignee:

GateField Corporation - Fremont CA

International Classification:

H01L 29788

US Classification:

257321

Abstract:

Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.

US Patent:

58941487, Apr 13, 1999

Filed:

Aug 9, 1996

Appl. No.:

8/708074

Inventors:

Jack Zezhong Peng - San Jose CA
Robert U. Broze - Santa Cruz CA
Kyung Joon Han - Cupertino CA
Victor Levchenko - Gilroy CA

Assignee:

GateField Corporation - Fremont CA

International Classification:

H01L 29788

US Classification:

257316

Abstract:

The present invention provides for an improved EPROM transistor cell which forms the programming portion of the programmable interconnect interconnect of an FPGA integrated circuit, and a method of manufacturing the EPROM cell. The EPROM cell has a floating gate disposed over a P region of the substrate. Aligned with one edge of the floating gate and at the surface of the substrate is a lightly doped P- region; on the opposite edge of the floating gate is a heavily doped N+ region. A control gate lies over the P-, P substrate and over the N+ region. N+ regions are formed at the opposite edges of the control gate. One N+ region is contiguous to the P- region and forms the source of the EPROM cell and the other N+ region is connected to the N+ region under the control gate and forms the drain of the EPROM cell. This structure allows for easy process control of the V. sub. T of the access transistor formed by the control gate and the P- surface, and of the space charge region formed by the P substrate and the N+ drain of the EPROM cell.