Vijay M Karamcheti

US Patent:

7774556, Aug 10, 2010

Filed:

Nov 5, 2007

Appl. No.:

11/935224

Inventors:

Vijay Karamcheti - Los Altos CA, US
Kenneth Alan Okin - Saratoga CA, US
Kumar Ganapathy - Los Altos CA, US
Ashish Singhai - Cupertino CA, US
Rajesh Parekh - Los Altos CA, US

Assignee:

Virident Systems Inc. - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711146, 711170

Abstract:

Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

US Patent:

7818489, Oct 19, 2010

Filed:

Nov 5, 2007

Appl. No.:

11/935275

Inventors:

Vijay Karamcheti - Los Altos CA, US
Kenneth A. Okin - Saratoga CA, US
Kumar Ganapathy - Los Altos CA, US
Ashish Singhai - Cupertino CA, US
Rajesh Parekh - Los Altos CA, US

Assignee:

Virident Systems Inc. - Milpitas CA

International Classification:

G06F 13/00

US Classification:

711101, 711103, 711146, 711170

Abstract:

Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.

US Patent:

7913055, Mar 22, 2011

Filed:

Nov 5, 2007

Appl. No.:

11/935254

Inventors:

Vijay Karamcheti - Los Altos CA, US
Kenneth A. Okin - Saratoga CA, US
Kumar Ganapathy - Los Altos CA, US
Ashish Singhai - Cupertino CA, US
Rajesh Parekh - Los Altos CA, US

Assignee:

Virident Systems Inc. - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711203, 711101

Abstract:

A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

US Patent:

7930513, Apr 19, 2011

Filed:

Nov 5, 2007

Appl. No.:

11/935281

Inventors:

Vijay Karamcheti - Los Altos CA, US
Kenneth A. Okin - Saratoga CA, US
Kumar Ganapathy - Los Altos CA, US
Ashish Singhai - Cupertino CA, US
Rajesh Parekh - Los Altos CA, US

Assignee:

Virident Systems Inc. - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711203, 711101, 711103, 711146, 711170

Abstract:

A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

US Patent:

8051253, Nov 1, 2011

Filed:

Sep 28, 2007

Appl. No.:

11/864763

Inventors:

Kenneth Alan Okin - Saratoga CA, US
George Moussa - Dublin CA, US
Kumar Ganapathy - Los Altos CA, US
Vijay Karamcheti - Los Altos CA, US
Rajesh Parekh - Los Altos CA, US

Assignee:

Virident Systems, Inc. - Milpitas CA

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711154, 711100, 711102, 711105

Abstract:

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

US Patent:

8074022, Dec 6, 2011

Filed:

Sep 28, 2007

Appl. No.:

11/864860

Inventors:

Kenneth Alan Okin - Saratoga CA, US
George Moussa - Dublin CA, US
Kumar Ganapathy - Los Altos CA, US
Vijay Karamcheti - Los Altos CA, US
Rajesh Parekh - Los Altos CA, US

Assignee:

Virident Systems, Inc. - Milpitas CA

International Classification:

G06F 12/00

US Classification:

711115, 711E12001

Abstract:

A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

US Patent:

8156288, Apr 10, 2012

Filed:

Aug 9, 2010

Appl. No.:

12/853135

Inventors:

Vijay Karamcheti - Los Altos CA, US
Kenneth A. Okin - Saratoga CA, US
Kumar Ganapathy - Los Altos CA, US
Ashish Singhai - Cupertino CA, US
Rajesh Parekh - Los Altos CA, US

Assignee:

Virident Systems Inc. - Milpitas CA

International Classification:

G06F 13/00

US Classification:

711146, 711170

Abstract:

Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.

US Patent:

8156299, Apr 10, 2012

Filed:

Oct 20, 2008

Appl. No.:

12/254767

Inventors:

Kenneth A. Okin - Saratoga CA, US
Vijay Karamcheti - Los Altos CA, US

Assignee:

Virident Systems Inc. - Milpitas CA

International Classification:

G06F 12/02

US Classification:

711165, 711101, 711103, 711170, 711203, 711E12002

Abstract:

A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.