Vikram Dadwal

US Patent:

20210117418, Apr 22, 2021

Filed:

Dec 23, 2020

Appl. No.:

17/133293

Inventors:

Vikram Dadwal - Chandler AZ, US
Christopher Shawn Michael Hall - Portland OR, US

International Classification:

G06F 16/2458
G06N 7/02
G06N 20/00
G05B 19/402

Abstract:

Various systems and methods for implementing time-aware general-purpose input output (TGPIO) for industrial control systems are described herein. A system includes edge detector circuitry to: detect rising or falling edges in an input signal; and store the rising or falling edges in a buffer along with a corresponding timestamp of the respective edge; and pattern match circuitry to: analyze the rising or falling edges in the buffer to identify a pattern of edges that matches a search pattern; and store timestamps corresponding to the pattern of edges in an event queue, the event queue used to notify a user application of the existence of the pattern of edges in the input signal.

US Patent:

20210111862, Apr 15, 2021

Filed:

Dec 23, 2020

Appl. No.:

17/132058

Inventors:

Vikram Dadwal - Chandler AZ, US
James Coleman - Mesa AZ, US
Alexander Slota - Mesa AZ, US

International Classification:

H04L 7/04
H04L 7/00

Abstract:

Systems and techniques for an heterogeneous clock management solution for industrial systems are described herein. In an example, a system includes a clock management circuit adapted to receive core timing information from a core of an integrated circuit. The clock management circuit is further adapted to correlate the core timing information with a reference clock. The clock management circuit is further adapted to output frequency and time offset of the reference clock to the core timing information. The system includes an execution circuit adapted to schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset. The execution circuit is further adapted to issue a command to execute the transaction at the scheduled time.