Vincent Fortin

US Patent:

6503824, Jan 7, 2003

Filed:

Oct 12, 2001

Appl. No.:

09/976392

Inventors:

Vincent Fortin - Santa Clara CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 214763

US Classification:

438622, 438675, 438676, 438680

Abstract:

Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

US Patent:

6670267, Dec 30, 2003

Filed:

Jun 13, 2001

Appl. No.:

09/881607

Inventors:

Vincent Fortin - Santa Clara CA

Assignee:

Mosel Vitelic Inc. - Hsin Chu

International Classification:

H01L 214763

US Classification:

438629, 438637, 438667, 438700, 257915

Abstract:

A tungsten-based interconnect is created by first providing a structure with an opening ( ) in a structure and then rounding the top edge of the opening. A titanium nitride layer ( ) is physically vapor deposited to a thickness less than 30 nm, typically less than 25 nm, over the structure and into the opening. Prior to depositing the titanium nitride layer, a titanium layer ( ) may be deposited over the structure and into the opening such that the later-formed titanium nitride layer contacts the titanium layer. In either case, the titanium nitride layer is heated, typically to at least 600Â C. , while being exposed to nitrogen and/or a nitrogen compound. A tungsten layer ( ) is subsequently chemically vapor deposited on the titanium nitride layer and into the opening.

US Patent:

6780086, Aug 24, 2004

Filed:

Oct 12, 2001

Appl. No.:

09/976331

Inventors:

Vincent Fortin - Santa Clara CA
Kuo-Chun Wu - San Jose CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

B24B 4900

US Classification:

451 8, 451 41

Abstract:

In a polishing process (e. g. CMP), the endpoint is declared after (a) detecting that the friction between the polishing tool and the structure being polished is rising, then (b) determining that the friction is falling, then (c) waiting for a predetermined period of time (which can be zero). This algorithm results in reduced over-polishing in some embodiments. Other embodiments are also described.

US Patent:

6787914, Sep 7, 2004

Filed:

Mar 27, 2002

Appl. No.:

10/109212

Inventors:

Vincent Fortin - Santa Clara CA

Assignee:

Mosel Vitelic, Inc. - Hsuin Chu

International Classification:

H01L 2348

US Classification:

257774, 257752, 257758, 257915, 438629, 438637, 438700

Abstract:

An interconnect for a substructure having an opening ( ) with a rounded perimetrical top edge ( ) includes a titanium nitride layer ( ) and a tungsten layer ( ). The titanium layer overlies the substructure, extends into the opening, has a substantially columnar grain structure, and is less than nm thick. The tungsten layer overlies/contacts the titanium nitride layer and extends into the opening. A titanium layer ( ) normally no more than 36 nm thick is typically situated between the substructure and the titanium nitride layer.

US Patent:

6835646, Dec 28, 2004

Filed:

Nov 19, 2002

Appl. No.:

10/300231

Inventors:

Vincent Fortin - Santa Clara CA

Assignee:

ProMOS Technologies, Inc. - Hsin-Chu

International Classification:

H01L 214763

US Classification:

438622, 438625, 438627, 438628, 438629, 438643, 438644, 438648, 438653, 438654, 438656, 438668, 438672, 438676, 438680, 438685

Abstract:

Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

US Patent:

6984574, Jan 10, 2006

Filed:

Jan 23, 2002

Appl. No.:

10/056154

Inventors:

Vincent Fortin - Santa Clara CA, US

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 21/425

US Classification:

438533, 438583, 438586, 438649, 438655, 438682

Abstract:

A cobalt silicide fabrication process entails first depositing a cobalt layer () on a silicon-containing EPROM region. A titanium layer () is formed over the cobalt layer by ionized physical vapor deposition (“IPVD”) to protect the cobalt layer from contaminant gases. Cobalt of the cobalt layer is reacted with silicon of the EPROM region to form a cobalt silicide layer () after which the titanium layer and any unreacted cobalt are removed. Use of IPVD to form the titanium layer by improves the step coverage to produce a better cobalt silicide layer.

US Patent:

6372671, Apr 16, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/652796

Inventors:

Vincent Fortin - Santa Clara CA

Assignee:

Zarlink Semiconductor Inc. - Ottawa

International Classification:

H01L 21469

US Classification:

438787, 427578, 427579, 427535, 438788

Abstract:

A dielectric layer of silica glass is formed by plasma enhanced chemical vapor deposition (PECVD) wherein a gaseous precursor of the dielectric layer is supplied to a deposition chamber in the presence of an electromagnetic field. The supply of the gaseous precursor is discontinued while continuing to maintain the electromagnetic field for a delay time exceeding 0. 5 seconds after the discontinuation of the supply of the gaseous precursor. This improves the hydrophilic properties of said film. A siloxane-based SOG film is deposited on the dielectric layer.