Vincenzo F Peluso

US Patent:

7084713, Aug 1, 2006

Filed:

Jan 25, 2005

Appl. No.:

11/043385

Inventors:

Vincenzo F. Peluso - San Diego CA, US

Assignee:

Qualcomm Inc. - San Diego CA

International Classification:

H03B 1/00
H03B 5/00
H03B 5/12

US Classification:

331179

Abstract:

A programmable capacitor bank includes multiple tuning elements. Each tuning element includes two tuning capacitors and a pass transistor that electrically connects or disconnects the capacitors to/from common nodes. For a thermometer decoded capacitor bank, the tuning capacitors for all tuning elements have equal capacitance. Each tuning element further includes at least one pull-up transistor that provides high bias voltage for the pass transistor and at least one pull-down transistor that provides low bias voltage for the pass transistor. The multiple tuning elements may be arranged in a ladder topology such that (1) the tuning elements are turned on in sequential order starting from one end of the ladder and going toward the other end of the ladder and (2) each tuning element receives biasing from a preceding tuning element and provides biasing to a succeeding tuning element. The capacitor bank may be used for VCOs and other circuits.

US Patent:

7406339, Jul 29, 2008

Filed:

Aug 5, 2002

Appl. No.:

10/213000

Inventors:

Seyfollah Bazarjani - San Diego CA, US
Sean Wang - San Diego CA, US
Vincenzo Peluso - San Diego CA, US
Louis Dominic Oliveira - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04M 1/00
H04B 1/38
H02M 11/00
H03F 3/45
G06G 7/28

US Classification:

4555691, 455 901, 455 902, 455351, 327103, 327334

Abstract:

An on-chip detection circuit automatically detects when an external switch has been activated. When the device is initialized, the detection circuit measures the operating current and coverts the information into an analog voltage. The analog voltage is then processed through an on-chip analog-to-digital converter and the digitized result is stored as a reference value. To sense the open and close action of the off-chip mechanical switch, the device then takes a sample of the operating current periodically, digitizes this information and compares the sampled value to the reference value. A change in value larger than some predetermined level indicates the external switch has been activated.

US Patent:

20030050085, Mar 13, 2003

Filed:

Apr 15, 2002

Appl. No.:

10/123841

Inventors:

Vincenzo Peluso - San Diego CA, US
Seyfollah Bazarjani - San Diego CA, US
Peter Shah - San Diego CA, US
James Jaffee - Solana Beach CA, US

International Classification:

H04Q007/20

US Classification:

455/522000, 455/070000

Abstract:

Techniques for processing incoming signals conforming to a plurality of standards or communication formats with a single baseband receive section are disclosed. In one aspect, a plurality of analog processing components are adjusted in response to a format select signal, set according to one of a plurality of supported formats or standards. In another aspect, the operating mode of an A/D converter is tuned in response to the format select signalIn yet another aspect, the response characteristics of a jammer filter are tuned in response to the format select signal. In yet another aspect, the adjustment of the plurality of analog processing components is carried out by varying the frequency of a sample clock in response to the format select signal. Various other aspects are also presented. These aspects have the benefit of allowing a single baseband receive section to be deployed to process analog signals conforming to a plurality of communications standards or formats, in a power and area efficient manner.

US Patent:

20070058324, Mar 15, 2007

Filed:

Apr 13, 2006

Appl. No.:

11/404471

Inventors:

Vincenzo Peluso - San Diego CA, US

International Classification:

H01G 4/255

US Classification:

361272000

Abstract:

The capacitor structure includes a first wall that serves a first terminal for a plurality of capacitors. The capacitor structure also includes a plurality of second walls that each serves as second terminals for a different one of the capacitors. In some instances, the first wall includes a plurality of first finger regions extending from a first common region and one or more of the first finger regions are at least partially positioned between different second walls.

US Patent:

6407689, Jun 18, 2002

Filed:

Nov 1, 2000

Appl. No.:

09/703647

Inventors:

Seyfollah Bazarjani - San Diego CA
Sean Wang - San Diego CA
Vincenzo Peluso - San Diego CA

Assignee:

Qualcomm, Incorporated - San Diego CA

International Classification:

H03M 300

US Classification:

341143, 341 77, 341132

Abstract:

A control mechanism that can be used to control a ADC to provide the required level of performance while reducing power consumption. The ADC is designed with multiple stages (i. e. , loops or sections), and provides improved performance (e. g. , higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e. g. , signal level) of the ADC input signal through a ADC that is similar to the ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal.

US Patent:

20160291619, Oct 6, 2016

Filed:

Mar 31, 2015

Appl. No.:

14/675262

Inventors:

- San Diego CA, US
Vincenzo Peluso - San Diego CA, US
Liangguo Shen - San Diego CA, US

International Classification:

G05F 1/575

Abstract:

In one embodiment, a low-dropout regulator comprises a pass transistor having a first terminal to receive an input voltage, a second terminal to provide an output voltage, and a gate terminal. A feedback circuit is coupled between the second terminal of the pass transistor and ground to generate a feedback voltage in response to the output voltage. A comparator has an output to generate a control voltage in response to the feedback voltage and a reference voltage. A switch is coupled between the output of the charge pump and the gate terminal of the pass transistor to selectively provide the control voltage to the gate terminal.

US Patent:

20160013765, Jan 14, 2016

Filed:

Jul 11, 2014

Appl. No.:

14/329615

Inventors:

- San Diego CA, US
Vincenzo Peluso - San Diego CA, US

International Classification:

H03F 3/00
H03F 3/45

Abstract:

A current sense circuit having a single opamp DC offset auto-zero capability that allows for continuous current sensing operation while at the same time providing for DC offset sensing and compensation. The single opamp design can operate in a first phase to sense and store a DC offset, while providing an output to drive an output stage of the current sense circuit. The single opamp design can operate in a second phase, using the sensed DC offset to generate an accurate output that can drive the output stage and which can be used in the first phase.

US Patent:

20160013804, Jan 14, 2016

Filed:

Jul 11, 2014

Appl. No.:

14/329661

Inventors:

- San Diego CA, US
Vincenzo F Peluso - San Diego CA, US

International Classification:

H03M 1/34
G01R 19/165

Abstract:

In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal.