Vivian H Liu

US Patent:

7448395, Nov 11, 2008

Filed:

Jul 19, 2004

Appl. No.:

10/894374

Inventors:

Freidoon Mehrad - Plano TX, US
Lindsey Hall - Plano TX, US
Vivian Liu - Garland TX, US
Clint Montgomery - Coppell TX, US
Scott Johnson - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B08B 6/00
C25F 1/00
C25F 3/30
C25F 5/00

US Classification:

134 13, 257382, 257769

Abstract:

The present invention substantially removes dry etch residue from a dry plasma etch process prior to depositing a cobalt layer on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation and then an extended cleaning operation that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation.

US Patent:

7112497, Sep 26, 2006

Filed:

Jun 25, 2004

Appl. No.:

10/877153

Inventors:

Freidoon Mehrad - Plano TX, US
Vivian Liu - Garland TX, US
Amitava Chatterjee - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438303, 438305, 257E21626

Abstract:

The present invention pertains to a multi-layer sidewall process () that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed () alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced () to establish second sidewall spacers having second widths which are smaller than the first widths.