Wai Hing Lo

US Patent:

7413996, Aug 19, 2008

Filed:

Apr 14, 2003

Appl. No.:

10/413051

Inventors:

Arvind Kamath - Mountain View CA, US
Wai Lo - Lake Oswego OR, US
Venkatesh Gopinath - Fremont CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/00

US Classification:

438745, 438689, 438369, 438694, 438766

Abstract:

A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.

US Patent:

7807580, Oct 5, 2010

Filed:

Apr 30, 2007

Appl. No.:

11/742003

Inventors:

Chungho Lee - Sunnyvale CA, US
Huaqiang Wu - Mountain View CA, US
Wai Lo - Palo Alto CA, US
Hiroyuki Kinoshita - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/302

US Classification:

438706, 438689, 438690, 438702, 216 37, 216 89

Abstract:

A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.

US Patent:

7829936, Nov 9, 2010

Filed:

Oct 17, 2007

Appl. No.:

11/873822

Inventors:

Minghao Shen - Sunnyvale CA, US
Shenqing Fang - Fremont CA, US
Wai Lo - Palo Alto CA, US
Christie R. K. Marrian - San Jose CA, US
Chungho Lee - Sunnyvale CA, US
Ning Cheng - San Jose CA, US
Fred Cheung - San Jose CA, US
Huaqiang Wu - Mountain View CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/331

US Classification:

257324, 257E21179, 257E21422, 257E2168, 438361

Abstract:

Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

US Patent:

7916529, Mar 29, 2011

Filed:

Feb 13, 2009

Appl. No.:

12/370932

Inventors:

Wai Lo - Palo Alto CA, US
Christie Marrian - San Jose CA, US
Tzu-Ning Fang - San Jose CA, US
Sameer Haddad - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

G11C 11/36

US Classification:

365175, 365115, 365100, 365148, 36523006, 36518904

Abstract:

A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

US Patent:

8202779, Jun 19, 2012

Filed:

Sep 27, 2010

Appl. No.:

12/891310

Inventors:

Shenqing Fang - Fremont CA, US
Angela Hui - Fremont CA, US
Gang Xue - Sunnyvale CA, US
Alexander Nickel - Santa Clara CA, US
Kashmir Sahota - Fremont CA, US
Scott Bell - San Jose CA, US
Chun Chen - San Jose CA, US
Wai Lo - Palo Alto CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438257, 438197, 257314, 257315

Abstract:

Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

US Patent:

8384146, Feb 26, 2013

Filed:

Mar 23, 2012

Appl. No.:

13/428848

Inventors:

Shenqing Fang - Fremont CA, US
Angela Hui - Fremont CA, US
Gang Xue - Sunnyvale CA, US
Alexander Nickel - Santa Clara CA, US
Kashmir Sahota - Fremont CA, US
Scott Bell - San Jose CA, US
Chun Chen - San Jose CA, US
Wai Lo - Palo Alto CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/76

US Classification:

257314, 257315, 438197, 438257

Abstract:

Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

US Patent:

8445913, May 21, 2013

Filed:

Oct 30, 2007

Appl. No.:

11/980213

Inventors:

Steven Avanzino - Cupertino CA, US
Tzu-Ning Fang - Palo Alto CA, US
Swaroop Kaza - Sunnyvale CA, US
Dongxiang Liao - Sunnyvale CA, US
Wai Lo - Palo Alto CA, US
Christie Marrian - San Jose CA, US
Sameer Haddad - San Jose CA, US

Assignee:

Spansion LLC - Sunnyvale CA

International Classification:

H01L 29/12

US Classification:

257 71, 257296, 257E27048

Abstract:

In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.

US Patent:

20110195348, Aug 11, 2011

Filed:

Feb 5, 2010

Appl. No.:

12/701391

Inventors:

Wai Lo - Palo Alto CA, US
Todd Lukanc - San Jose CA, US
Christie Marrian - San Jose CA, US

International Classification:

G03F 1/00
B05C 11/00

US Classification:

430 5, 118697

Abstract:

Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.