Walid M Hafez from Portland, OR, age 45

Dr. Walid M Hafez, Quincy IL - MD (Doctor of Medicine)

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Specialties:

Sleep Medicine
Sleep Medicine Psychiatry & Neurology

Address:

Blessing Physician Services
927 Broadway St Suite 302, Quincy, IL 62301
(217)2246423 (Phone)

Procedures:

EEG (Electroencephalogram)
EMG (Electromyography)

Conditions:

Alzheimer's Disease
Ataxia
Bell's Palsy
Brachial Plexus Palsy
Brain and Nervous System Cancer (incl. Gliomas, Astrocytoma, Schwannoma, Medulloblastoma, Chordoma)
Brain Injury
Carpal Tunnel Syndrome
Cerebral Aneurysm
Cerebral Artery Thrombosis
Cerebral Vascular Disease
Cerebrovascular Disease
Chiari's Deformity
Concussion
Convulsions
Cranial Trauma
Dementia
Diabetic Polyneuropathy
Diplopia
Dystonia
Epilepsy
Essential Tremor
Gait Abnormality
Headache
Huntington's Disease
Hydrocephalus
Inflammatory and Toxic Neuropathy
Insomnia
Intervertebral Disc Herniation
Low Back Pain
Lyme Disease
Meningiomas
Migraine
Multiple Sclerosis (MS)
Muscular Dystrophy (MD)
Myasthenia Gravis
Myoclonus
Narcolepsy and Cataplexy
Nerve Sheath Tumors
Normal Pressure Hydrocephalus
Parkinsonism
Parkinson's Disease
Peripheral Nerve Disorders
Peripheral Neuropathy
Post-Concussion Syndrome
Progressive Supranuclear Palsy (PSP)
Pseudotumor Cerebri
Radiculopathy (not Due to Disc Displacement)
Reflex Sympathetic Dystrophy
Restless Legs Syndrome
Sleep Apnea
Spina Bifida
Spinal Stenosis
Stroke
Syncope
Tension Headache
Transient Ischemic Attack (TIA)
Tremor
Trigeminal Neuralgia
Tuberous Sclerosis
Vasculitis
Vertigo
Visual Field Defects

Certifications:

Neurology, 1979
Sleep Medicine, 2011

Awards:

Healthgrades Honor Roll

Languages:

English

Hospitals:

Blessing Physician Services
927 Broadway St Suite 302, Quincy, IL 62301

Blessing Hospital - 11th Street
Broadway At 11Th Street And 14Th Street, Quincy, IL 62305

Education:

Medical School
American University of Beirut / Faculty of Medicine
Medical School
Berkshire Med Center
Medical School
University Iowa Hosps and Clinics

Walid M. Hafez

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Specialties:

Neurology

Work:

Family Medicine AssociatesBlessing Physician Services
927 Broadway St STE 302, Quincy, IL 62301
(217)2246423 (phone), (217)2215581 (fax)

Education:

Medical School
American University of Beirut, Faculty of Medicine, Beirut, Lebanon
Graduated: 1972

Procedures:

Lumbar Puncture
Neurological Testing
Sleep and EEG Testing

Conditions:

Alzheimer's Disease
Bell's Palsy
Carpel Tunnel Syndrome
Dementia
Diabetic Peripheral Neuropathy

Languages:

English
Spanish

Description:

Dr. Hafez graduated from the American University of Beirut, Faculty of Medicine, Beirut, Lebanon in 1972. He works in Quincy, IL and specializes in Neurology. Dr. Hafez is affiliated with Blessing Hospital.

Walid Hafez, Quincy IL

Work:

Blessing Physician Services
927 Broadway St, Quincy, IL 62301
Midwest Family Medical Care
630 Locust St, Carthage, IL 62321

Walid M Hafez, Quincy IL

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Specialties:

Neurologist

Address:

927 Broadway St, Quincy, IL 62301

Board certifications:

American Board of Psychiatry and Neurology Certification in Neurology (Psychiatry and Neurology)
American Board of Psychiatry and Neurology Sub-certificate in Sleep Medicine (Psychiatry and Neurology)

Milt Feng

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In 2003, Milton Feng and his graduate students Walid Hafez and Jie-Wei Lai broke the record for the world's fastest transistor. Their device, made of indium ...

Walid Hafez

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Skills:

Intel

Us Patents

Method Of Forming Programmable Anti-Fuse Element
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US Patent:

8101471, Jan 24, 2012
Filed:

Dec 30, 2008
Appl. No.:

12/319104
Inventors:

Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Chetan Prasad - Hillsboro OR, US
Sangwoo Pae - Beaverton OR, US
Zhanping Chen - Portland OR, US
Anisur Rahman - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 21/82
US Classification:

438132, 438131, 438215, 438281, 257E21592
Abstract:

A programmable anti-fuse element includes a substrate (), an N-well () in the substrate, an electrically insulating layer () over the N-well, and a gate electrode () over the electrically insulating layer. The gate electrode has n-type doping so that the N-well is able to substantially contain within its boundaries a current generated following a programming event of the programmable anti-fuse element. In the same or another embodiment, a twice-programmable fuse element () includes a metal gate fuse () and an oxide anti-fuse () such as the programmable anti-fuse element just described.

Penetrating Implant For Forming A Semiconductor Device
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US Patent:

8426927, Apr 23, 2013
Filed:

May 13, 2011
Appl. No.:

13/107783
Inventors:

Giuseppe Curello - Portland OR, US
Ian R. Post - Portland OR, US
Nick Lindert - Beaverton OR, US
Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Mark T. Bohr - Aloha OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 29/66
H01L 21/02
US Classification:

257402, 257 48, 257607, 257E29109, 257E29255
Abstract:

A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Memory Cell Using Bti Effects In High-K Metal Gate Mos
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US Patent:

8432751, Apr 30, 2013
Filed:

Dec 22, 2010
Appl. No.:

12/976630
Inventors:

Walid M. Hafez - Portland OR, US
Anisur Rahman - Hillsboro OR, US
Chia-Hong Jan - Portland OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 7/00
US Classification:

36518916, 36518915, 365189011, 36518907, 36518909, 36518503, 36518514, 36518518, 36518519, 36518521, 36518523
Abstract:

Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

High-Voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same
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US Patent:

8487376, Jul 16, 2013
Filed:

Aug 18, 2010
Appl. No.:

12/858770
Inventors:

Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Anisur Rahman - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 29/76
US Classification:

257337, 257E2159, 257E2706, 257408
Abstract:

An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

Methods Of Forming Secured Metal Gate Antifuse Structures
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US Patent:

8618613, Dec 31, 2013
Filed:

Mar 31, 2011
Appl. No.:

13/077681
Inventors:

Xianghong Tong - Hillsboro OR, US
Zhanping Chen - Hillsboro OR, US
Walid M. Hafez - Portland OR, US
Zhiyong Ma - Hillsboro OR, US
Sarvesh H. Kulkarni - Hillsboro OR, US
Kevin X. Zhang - Portland OR, US
Matthew B. Pedersen - Beaverton OR, US
Kevin D. Johnson - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 27/11
H01L 21/02
H01L 23/52
US Classification:

257379, 257408, 257529, 257530
Abstract:

Methods of forming and using a microelectronic structure are described. Embodiments include forming a diode between a metal fuse gate and a PMOS device, wherein the diode is disposed between a contact of the metal fuse gate and a contact of the PMOS device, and wherein the diode couples the contact of the metal fuse gate to the contact of the PMOS device.

Light Emitting Device And Method
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US Patent:

20050040432, Feb 24, 2005
Filed:

Aug 22, 2003
Appl. No.:

10/646457
Inventors:

Milton Feng - Champaign IL, US
Nick Holonyak - Urbana IL, US
Walid Hafez - Champaign IL, US
International Classification:

H01L031/0328
US Classification:

257198000
Abstract:

A method for producing controllable light emission from a semiconductor device includes the following steps: providing a heterojunction bipolar transistor device that includes collector, base, and emitter regions; and applying electrical signals across terminals coupled with the collector, base, and emitter regions to cause light emission by radiative recombination in the base region. In a disclosed embodiment, the step of applying electrical signals includes applying a collector-to-emitter voltage and modulating light output by applying a modulating base current.

Multi-Gate Transistor With Strained Body
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US Patent:

20090001415, Jan 1, 2009
Filed:

Jun 30, 2007
Appl. No.:

11/772199
Inventors:

Nick Lindert - Beaverton OR, US
Walid Mac Hafez - Portland OR, US
International Classification:

H01L 29/778
H01L 21/335
US Classification:

257190, 438164, 257E21403, 257E29246
Abstract:

A semiconductor device comprises a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate, wherein the semiconductor body comprises a silicon alloy core having a top surface and laterally opposite sidewalls formed on a silicon fin structure, and a silicon shell layer formed on the top surface and the laterally opposite sidewalls of the silicon alloy core, wherein the silicon alloy core imparts a strain on the silicon shell layer. The semiconductor device further comprises a gate dielectric layer formed on the top surface and the laterally opposite sidewalls of the semiconductor body and a gate electrode formed on the gate dielectric layer.

Penetrating Implant For Forming A Semiconductor Device
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US Patent:

20090242998, Oct 1, 2009
Filed:

Mar 31, 2008
Appl. No.:

12/059455
Inventors:

Giuseppe Curello - Portland OR, US
Ian R. Post - Portland OR, US
Nick Lindert - Beaverton OR, US
Walid M. Hafez - Portland OR, US
Chia-Hong Jan - Portland OR, US
Mark T. Bohr - Aloha OR, US
International Classification:

H01L 29/78
H01L 21/336
H01L 21/8234
US Classification:

257409, 438294, 438275, 257E29019, 257E29255, 257E21433, 257E21628
Abstract:

A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Walid M Hafez

Walid Hafez Phones & Addresses

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Medicine Doctors

Dr. Walid M Hafez, Quincy IL - MD (Doctor of Medicine)

Walid M. Hafez

Walid Hafez, Quincy IL

Walid M Hafez, Quincy IL

Wikipedia

Milt Feng

Resumes

Walid Hafez

Us Patents

Method Of Forming Programmable Anti-Fuse Element

Penetrating Implant For Forming A Semiconductor Device

Memory Cell Using Bti Effects In High-K Metal Gate Mos

High-Voltage Transistor Architectures, Processes Of Forming Same, And Systems Containing Same

Methods Of Forming Secured Metal Gate Antifuse Structures

Light Emitting Device And Method

Multi-Gate Transistor With Strained Body

Penetrating Implant For Forming A Semiconductor Device

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