Wallace P Printz

US Patent:

8568964, Oct 29, 2013

Filed:

Apr 27, 2009

Appl. No.:

12/430203

Inventors:

Carlos A. Fonseca - Fishkill NY, US
Mark Somervell - Austin TX, US
Steven Scheer - Austin TX, US
Wallace P. Printz - Austin TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G03F 7/30

US Classification:

430394, 430311

Abstract:

A method and system for patterning a substrate using a dual tone development process is described. The method and system comprise a flood exposure of the substrate to improve process latitude for the dual tone development process.

US Patent:

8574810, Nov 5, 2013

Filed:

Dec 11, 2009

Appl. No.:

12/636211

Inventors:

Carlos A. Fonseca - Fishkill NY, US
Mark Somervell - Austin TX, US
Steven Scheer - Austin TX, US
Wallace P. Printz - Austin TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G03F 7/26
G03F 7/20

US Classification:

4302701, 430330, 430394

Abstract:

A method and system for patterning a substrate using a lithographic process, such as a dual tone development process, is described. The method comprises use of at least one photo-activated acid enhancement component to improve process latitude for the dual tone development process.

US Patent:

20100154826, Jun 24, 2010

Filed:

Dec 19, 2008

Appl. No.:

12/339273

Inventors:

Wallace P. Printz - Austin TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

B08B 7/04

US Classification:

134 18

Abstract:

Embodiments of the invention provide optimized rinse systems and methods for providing rinsing solutions to one or more surfaces of semiconductor wafers. Embodiments of the invention may be applied to process wafers at different points in a manufacturing cycle, and the wafers can include one or more metal layers.

US Patent:

20100273111, Oct 28, 2010

Filed:

Sep 22, 2009

Appl. No.:

12/564755

Inventors:

Carlos A. FONSECA - Fishkill NY, US
Mark SOMERVELL - Austin TX, US
Steven SCHEER - Austin TX, US
Wallace P. PRINTZ - Austin TX, US

Assignee:

TOKYO ELECTRON LIMITED - Tokyo

International Classification:

G03F 7/20

US Classification:

430325

Abstract:

A method and system for patterning a substrate using a dual tone development process is described. The method comprises use of plural photo-acid generators with or without a flood exposure of the substrate to improve process latitude for the dual tone development process.

US Patent:

20120045721, Feb 23, 2012

Filed:

Aug 18, 2010

Appl. No.:

12/858919

Inventors:

Wallace P. Printz - Austin TX, US
Steven Scheer - Austin TX, US

Assignee:

Tokyo Electron Limited - Tokyo

International Classification:

G03F 7/20

US Classification:

430312, 430324

Abstract:

The invention can provide a method of processing a substrate using Double-Patterned-Shadow (D-P-S) processing sequences that can include (D-P-S) creation procedures, (D-P-S) evaluation procedures, and (D-P-S) transfer sequences. The (D-P-S) creation procedures can include deposition procedures, activation procedures, de-protecting procedures, sidewall angle (SWA) correction procedure, and Double Patterned (DP) developing procedures.

US Patent:

20120045722, Feb 23, 2012

Filed:

Aug 18, 2010

Appl. No.:

12/858982

Inventors:

Wallace P. Printz - Austin TX, US
Steven Scheer - Austin TX, US

International Classification:

G03F 7/20

US Classification:

430325

Abstract:

The invention can provide a method of processing a substrate using Double-Patterned-Shadow (D-P-S) processing sequences that can include (D-P-S) creation procedures, (D-P-S) evaluation procedures, and (D-P-S) transfer sequences. The (D-P-S) creation procedures can include deposition procedures, activation procedures, de-protecting procedures, sidewall angle (SWA) correction procedure, and Double Patterned (DP) developing procedures.

US Patent:

20120247505, Oct 4, 2012

Filed:

Mar 30, 2011

Appl. No.:

13/076396

Inventors:

IAN J. BROWN - AUSTIN TX, US
WALLACE P. PRINTZ - AUSTIN TX, US

Assignee:

TOKYO ELECTRON LIMITED - TOKYO

International Classification:

B08B 3/08
B08B 13/00
H01L 21/308

US Classification:

134 3, 15634519, 134 36

Abstract:

Provided is a method and system for increasing etch rate and etch selectivity of a masking layer on a substrate in an etch treatment system, the etch treatment system configured for single substrate processing. The method comprises obtaining a supply of steam water vapor mixture at elevated pressure, obtaining a supply of treatment liquid for selectively etching the masking layer over the silicon or silicon oxide at a set etch selectivity ratio, placing the substrate into the etch processing chamber, combining the treatment liquid and the steam water vapor mixture, and injecting the combined treatment liquid and the steam water vapor mixture into the etch processing chamber, wherein the flow of the combined treatment liquid and the steam water vapor mixture is controlled to maintain a set etch rate and a set etch selectivity ratio of the masking layer to silicon or silicon oxide.

US Patent:

20120248061, Oct 4, 2012

Filed:

Mar 30, 2011

Appl. No.:

13/076272

Inventors:

IAN J. BROWN - AUSTIN TX, US
WALLACE P. PRINTZ - AUSTIN TX, US

Assignee:

TOKYO ELECTRON LIMITED - TOKYO

International Classification:

C23F 1/02
C23F 1/16
C23F 1/08

US Classification:

216 12, 15634511

Abstract:

Provided is a method and system for increasing etch rate and etch selectivity of a masking layer on a substrate, wherein the system comprises a plurality of substrates containing the masking layer and a layer of silicon or silicon oxide, an etch processing chamber configured to process the plurality of substrates, the processing chamber containing a treatment liquid for etching the masking layer, and a boiling apparatus coupled to the processing chamber and configured to generate a supply of steam water vapor mixture at elevated pressure, wherein the steam water vapor mixture is introduced into the processing chamber at a controlled rate to maintain a selected target etch rate and a target etch selectivity ratio of the masking layer to silicon or silicon oxide.