Walter A Lee

US Patent:

8181168, May 15, 2012

Filed:

Feb 7, 2008

Appl. No.:

12/028007

Inventors:

Walter Lee - Framingham MA, US
Robert A. Gottlieb - Westford MA, US
Vineet Soni - Union City CA, US
Anant Agarwal - Weston MA, US
Richard Schooler - Cambridge MA, US

Assignee:

Tilera Corporation - Westborough MA

International Classification:

G06F 9/445

US Classification:

717149

Abstract:

A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to different portions of a program, the subsets of instructions being related according to a control flow graph; forming one or more memory analysis regions that include one or more of the subsets of instructions, where each subset of instructions is included in a single memory analysis region; analyzing each memory analysis region to partition memory objects and instructions that access the memory objects into equivalence classes such that instructions within an equivalence class only access objects in the same equivalence class; and assigning memory access instructions a given equivalence class to one of the computation units for execution on the assigned computation unit.

US Patent:

8250556, Aug 21, 2012

Filed:

Feb 7, 2008

Appl. No.:

12/028003

Inventors:

Walter Lee - Framingham MA, US
Robert A. Gottlieb - Westford MA, US
Vineet Soni - Union City CA, US
Anant Agarwal - Weston MA, US
Richard Schooler - Cambridge MA, US

Assignee:

Tilera Corporation - Westborough MA

International Classification:

G06F 9/44
G06F 9/45

US Classification:

717159, 717132, 717151, 717161

Abstract:

A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving an initial partitioning of instructions into initial subsets corresponding to different portions of a program; forming a refined partitioning of the instructions into refined subsets each including one or more of the initial subsets, including determining whether to combine a first subset and a second subset to form a third subset according to a comparison of a communication cost between the first subset and second subset and a load cost of the third subset that is based at least in part on a number of instructions issued per cycle by a computation unit; and assigning each refined subset of instructions to one of the computation units for execution on the assigned computation unit.

US Patent:

8291400, Oct 16, 2012

Filed:

Feb 7, 2008

Appl. No.:

12/028005

Inventors:

Walter Lee - Framingham MA, US
Robert A. Gottlieb - Westford MA, US
Vineet Soni - Union City CA, US
Anant Agarwal - Weston MA, US
Richard Schooler - Cambridge MA, US

Assignee:

Tilera Corporation - Westborough CA

International Classification:

G06F 9/45
G06F 13/00
G06F 13/28
G06F 9/44

US Classification:

717161, 711167, 717106

Abstract:

A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises receiving subsets of instructions corresponding to different portions of a program, each subset assigned to one of the computation units; scheduling instructions in a given subset for execution on the assigned computation unit, including scheduling communication instructions that send to or receive from a different computation unit over the interconnection network; allocating registers in a given computation unit for storing values accessed by instructions in a subset assigned to the given computation unit; and scheduling instructions after allocating registers to account for spills of values stored in allocated register to memory, preserving the order of communication instructions scheduled before allocating registers.