Wayne Louis Shepherd

US Patent:

45595054, Dec 17, 1985

Filed:

Jan 4, 1983

Appl. No.:

6/455454

Inventors:

Jose I. Suarez - Miami FL
James S. Irwin - Ft. Lauderdale FL
Wayne P. Shepherd - Sunrise FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 700

US Classification:

331 1A

Abstract:

A frequency synthesizer is provided including a reference frequency generator coupled to one input of a phase detector. The output of the phase detector is coupled via a pair of alternatingly connected filters through a voltage controlled oscillator and a divider circuit to the remaining input of the phase detector to form a phase locked loop. The first filter of the pair is designated for operation on a main channel frequency while the remaining filter is designated for operation on a priority channel frequency. The capacitive elements of each respective filter remain fully charged up for operation on their respective frequencies and thus when such filters are alternately switched between to change frequency from the main channel to the priority channel, the capacitive elements need not be charged to new levels to accommodate such frequency change. Thus, switching between a main channel and a priority channel is accomplished in a minimal amount of time with a significant reduction in frequency synthesizer energy requirements.

US Patent:

47136316, Dec 15, 1987

Filed:

Jan 6, 1986

Appl. No.:

6/816589

Inventors:

Ralph T. Enderby - Sunrise FL
Enrique Ferrer - Miami FL
Wayne P. Shepherd - Sunrise FL

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03B 508
H03H 512
H03L 718

US Classification:

331 36C

Abstract:

A variable capacitance circuit includes a varactor having an anode side and a cathode side. A first variable bias voltage is applied to one of the sides and one of a plurality of voltages is applied as a second bias voltage to the other side for controlling the capacitance of the varactor. A voltage multiplier circuit connected to a voltage divider network is used for supplying the plurality of voltages. A decoder is responsive to input signals for selecting and applying one of the multiple voltage outputs. The variable capacitance circuit is used in a voltage controlled oscillator of a frequency synthesizer for providing extended frequency range.

US Patent:

49947680, Feb 19, 1991

Filed:

Mar 26, 1990

Appl. No.:

7/499102

Inventors:

Wayne P. Shepherd - Sunrise FL
Darrell E. Davis - Sunrise FL
Frederick L. Martin - Gainesville FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03C 309

US Classification:

332127

Abstract:

A frequency synthesizer (10) for providing a modulated output signal (fo) includes a reference frequency signal (fr) and a voltage controlled oscillator (14). For dividing the frequency of the output signal from the voltage controlled oscillator (14) by a divisor, a programmable divider (16) is coupled to the output of the voltage controlled oscillator (14). To produce a phase-locked loop in which the frequency of the output signal from the voltage controlled oscillator (14) is equal to the frequency of the reference frequency (fr) signal multiplied by the divisor, a phase detector (12 ) having a first input coupled to the reference frequency signal (fr), a second input coupled to the output of the programmable divider (16), and an output coupled to the input of the voltage controlled oscillator (14) is also provided. A first integrator (24) for integrating a modulating signal provides an integrated signal and a first control signal. Similarly, a second integrator (25) coupled to the first integrator (24) for integrating the integrated signal provides a second control signal.

US Patent:

50217542, Jun 4, 1991

Filed:

Jul 16, 1990

Appl. No.:

7/553472

Inventors:

Wayne P. Shepherd - Sunrise FL
Darrell E. Davis - Sunrise FL
Wan F. Tay - Coral Springs FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03C 300
H03L 7197

US Classification:

332128

Abstract:

A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.

US Patent:

49806530, Dec 25, 1990

Filed:

Sep 5, 1989

Appl. No.:

7/402715

Inventors:

Wayne P. Shepherd - Sunrise FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 718

US Classification:

331 16

Abstract:

A phase locked loop (100) with a sample and hold phase detector (106) with adjustable gain. A switching circuit adjusts the slew rate of the phase detector by either introducing additional ramp capacitance (122) in the phase detector or by increasing the current for charging the ramp capacitor (116).