Wayne D Tran

US Patent:

7225318, May 29, 2007

Filed:

Oct 8, 2003

Appl. No.:

10/681070

Inventors:

Wayne Tran - Folsom CA, US
Henry Wong - Rancho Cordova CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711213, 711137, 712207

Abstract:

In a continuous burst memory read operation, a dynamic prefetch circuit compares a prefetched address with a received address. If the compared addresses are identical, the prefetched address is applied to the memory; else the prefetched address is preempted by the received address, the received address is coupled to the memory, and output data corresponding to the prefetched address is interrupted.

US Patent:

20190180830, Jun 13, 2019

Filed:

Dec 22, 2017

Appl. No.:

15/852785

Inventors:

- Santa Clara CA, US
Wayne Tran - Folsom CA, US

International Classification:

G11C 16/34
G11C 16/10
G11C 29/00

Abstract:

An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.

US Patent:

20190102296, Apr 4, 2019

Filed:

Sep 29, 2017

Appl. No.:

15/721237

Inventors:

- Santa Clara CA, US
Aliasgar S. MADRASWALA - Folsom CA, US
Wayne D. TRAN - Folsom CA, US

International Classification:

G06F 12/0804
G06F 3/06

Abstract:

In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

US Patent:

20190041947, Feb 7, 2019

Filed:

Jun 28, 2018

Appl. No.:

16/022675

Inventors:

- Santa Clara CA, US
Wayne Tran - Folsom CA, US
Vishal Mannapur - Folsom CA, US
Anthony Giardina - Colfax CA, US

International Classification:

G06F 1/32
G06F 13/42

Abstract:

Technologies for dynamically managing a power state of a first endpoint device and a second endpoint device that are operatively coupled to a data bus of a compute device include communication monitor circuitry and power state manager circuitry. The communication monitor circuitry is configured to detect an activation signal on the data bus. The power state manager circuitry is configured to activate, in response to detection of the activation signal, the first and second endpoint devices that are operatively coupled to the data bus into a high power state from a low power state, determine, in response to activation of the first and second endpoint devices, which activated endpoint device is requested to perform work associated with the activation signal, and operate, in response to determination that the second endpoint device has no pending work to perform, the second endpoint device to return to the low power state.

US Patent:

20170315866, Nov 2, 2017

Filed:

Feb 27, 2017

Appl. No.:

15/443707

Inventors:

- SANTA CLARA CA, US
WAYNE D. TRAN - FOLSOM CA, US
ALIASGAR S. MADRASWALA - FOLSOM CA, US
SUNGHO PARK - FOLSOM CA, US

Assignee:

INTEL CORPORATION - SANTA CLARA CA

International Classification:

G06F 11/10
G11C 16/34
G11C 16/26
G06F 11/10
G11C 29/04
G11C 11/56

Abstract:

An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.

US Patent:

20140089764, Mar 27, 2014

Filed:

Mar 29, 2012

Appl. No.:

13/977012

Inventors:

Matthew Goldman - Folsom CA, US
Wayne D. Tran - Folsom CA, US
Aliasgar S. Madraswala - Folsom CA, US
Sungho Park - Folsom CA, US

International Classification:

G06F 11/10

US Classification:

714773

Abstract:

An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.