Wei Lai Lu

US Patent:

7858965, Dec 28, 2010

Filed:

May 25, 2007

Appl. No.:

11/807186

Inventors:

Wei Lu - Ann Arbor MI, US
Jie Xiang - Pasadena CA, US
Yue Wu - El Cerrito CA, US
Brian P. Timko - Cambridge MA, US
Hao Yan - Cambridge MA, US
Charles M. Lieber - Lexington MA, US

Assignee:

President and Fellows of Harvard College - Cambridge MA

International Classification:

H01L 29/778

US Classification:

257 24, 257 19, 257 20, 257E2907, 257194

Abstract:

The present invention generally relates to nanoscale heterostructures and, in some cases, to nanowire heterostructures exhibiting ballistic transport, and/or to metal-semiconductor junctions that that exhibit no or reduced Schottky barriers. One aspect of the invention provides a solid nanowire having a core and a shell, both of which are essentially undoped. For example, in one embodiment, the core may consist essentially of undoped germanium and the shell may consist essentially of undoped silicon. Carriers are injected into the nanowire, which can be ballistically transported through the nanowire. In other embodiments, however, the invention is not limited to solid nanowires, and other configurations, involving other nanoscale wires, are also contemplated within the scope of the present invention. Yet another aspect of the invention provides a junction between a metal and a nanoscale wire that exhibit no or reduced Schottky barriers. As a non-limiting example, a nanoscale wire having a core and a shell may be in physical contact with a metal electrode, such that the Schottky barrier to the core is reduced or eliminated.

US Patent:

8071972, Dec 6, 2011

Filed:

Oct 20, 2009

Appl. No.:

12/582086

Inventors:

Wei Lu - Ann Arbor MI, US
Sung Hyun Jo - Ann Arbor MI, US

Assignee:

The Regents of the University of Michigan - Ann Arbor MI

International Classification:

H01L 29/06
H01L 21/82

US Classification:

257 5, 257E47001, 257E21575, 438128

Abstract:

The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.

US Patent:

8351241, Jan 8, 2013

Filed:

Jun 29, 2010

Appl. No.:

12/826653

Inventors:

Wei Lu - Ann Arbor MI, US
Sung Hyun Jo - Sunnyvale CA, US

Assignee:

The Regents of the University of Michigan - Ann Arbor MI

International Classification:

G11C 11/00
G11C 11/15

US Classification:

365148, 365163, 365175

Abstract:

A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.

US Patent:

8374018, Feb 12, 2013

Filed:

Jul 9, 2010

Appl. No.:

12/833898

Inventors:

Wei Lu - Ann Arbor MI, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

G11C 11/00
H01L 47/00

US Classification:

365148, 365163, 257 2, 257 5

Abstract:

A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell.

US Patent:

8441835, May 14, 2013

Filed:

Jun 11, 2010

Appl. No.:

12/814410

Inventors:

Sung Hyun Jo - Sunnyvale CA, US
Hagop Nazarian - San Jose CA, US
Wei Lu - Ann Arbor MI, US

Assignee:

Crossbar, Inc. - Menlo Park CA

International Classification:

G11C 11/00

US Classification:

365148, 365158

Abstract:

A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.

US Patent:

8502185, Aug 6, 2013

Filed:

May 31, 2011

Appl. No.:

13/149757

Inventors:

Wei Lu - Ann Arbor MI, US
Sung Hyun Jo - Sunnyvale CA, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

H01L 47/00
H01L 27/10
H01L 45/00

US Classification:

257 4, 257 3, 257 5, 257296, 257E45001, 257E45002, 257E47001, 257E47002, 365148, 365163, 438 95, 438 97, 438102, 438152

Abstract:

A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

US Patent:

8599601, Dec 3, 2013

Filed:

Feb 15, 2013

Appl. No.:

13/769152

Inventors:

Hagop Nazarian - San Jose CA, US
Wei Lu - Ann Arbor MI, US

Assignee:

Crossbar, Inc. - Santa Clara CA

International Classification:

G11C 11/00

US Classification:

365148, 365158

Abstract:

A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.

US Patent:

20090004852, Jan 1, 2009

Filed:

Dec 9, 2005

Appl. No.:

10/588833

Inventors:

Charles M. Lieber - Lexington MA, US
Yue Wu - Cambridge MA, US
Jie Xiang - Cambridge MA, US
Chen Yang - Somerville MA, US
Wei Lu - Ann Arbor MI, US

Assignee:

President and Fellows of Havard College - Cambridge MA

International Classification:

H01L 21/44

US Classification:

438664, 257E21199

Abstract:

A network element (), such as a Packet Data Serving Node, detects () a change in operational status of a mobile station during a communication session and, in response to detecting such a change, automatically increases () memory capacity as is available to support additional communication sessions while simultaneously persisting at least some session information for potential subsequent use during the communication session. For example, this response can occur upon detecting that a mobile station has changed from an active to a dormant status. Then, upon returning to an active status, the network element can use the persisted information to facilitate rapid reconstruction of infrastructure support for the mobile station's call participation.