Weiqiang L Ma

US Patent:

57938040, Aug 11, 1998

Filed:

Mar 28, 1997

Appl. No.:

8/827537

Inventors:

Weiqiang Ma - Tempe AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 138

US Classification:

375222

Abstract:

A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated remotely using a clock having a frequency that may be different than the frequency of the clock in the receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A. gtoreq. 1. The interpolator processes L-B samples per block and passes them on to the buffer, where B. gtoreq. The buffer passes L samples per block to the modem processor. If L samples are not available, the processor skips a cycle.

US Patent:

59404370, Aug 17, 1999

Filed:

Feb 7, 1997

Appl. No.:

8/796054

Inventors:

Weiqiang Ma - Tempe AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 140
H04L 700

US Classification:

375222

Abstract:

A system and method for limiting the processing load on a digital processor in a block processing modem that is receiving data that was generated from the digital to analog clock of the remote transmit modem having a frequency that may be different than the frequency of the analog to digital clock in the local receiving modem. The receiving modem includes a digital processor having a desired processing capacity reserved for block processing of L samples of data per block period, an analog to digital converter for converting the received data into samples, an interpolator and a buffer memory. The analog to digital converter outputs L-A samples per block and passes them to the interpolator, where A. gtoreq. 1. The interpolator processes L-B samples per block and passes them on to the buffer, where B. gtoreq. The buffer passes L samples per block to the modem processor.

US Patent:

61545023, Nov 28, 2000

Filed:

Aug 22, 1996

Appl. No.:

8/701695

Inventors:

Zdenek Brun - Phoenix AZ
Weiqiang Ma - Tempe AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 2302
H03D 100

US Classification:

375261

Abstract:

Data represented by a received point which is not within a boundary of a signal constellation having a set of points is obtained by comparing the received point to less than all of the points on a boundary of the signal constellation. In an embodiment, the received point is compared to no more than two points on the boundary which have been predetermined to be the closest to the received point.

US Patent:

20140282579, Sep 18, 2014

Filed:

Mar 14, 2013

Appl. No.:

13/829118

Inventors:

David A. Smiley - Chandler AZ, US
Naveen Lakkakula - Chandler AZ, US
Weiqiang Ma - Chandler AZ, US
Justin B. Diether - Phoenix AZ, US
Nitin N. Garegrat - Chandler AZ, US

International Classification:

G06F 9/50

US Classification:

718104

Abstract:

A processing engine implementing job arbitration with ordering status is disclosed. A method of the disclosure includes receiving, by a job assigner communicably coupled to a plurality of processors, availability status from a plurality of job rings, availability status from the plurality of processors, and job entry completion status from an order manager, identifying, based on the received job entry completion status, a set of job rings from the plurality of job rings that do not exceed threshold conditions maintained by the job assigner, selecting, from the identified set of job rings, a job ring from which to pull a job entry for assignment, wherein the selecting is based on the received availability status of the plurality of job rings, and selecting, based on the received availability status of the plurality of processors, a processor to receive the assignment of the job entry for processing.