Wen Long Wu from San Leandro, CA, age 40

Isbn (Books And Publications)

Ancient Sculpture

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Author
Wen Wu

ISBN #
7119030493

Medicine Doctors

Dr. Wen Wu, Foster City CA - DDS (Doctor of Dental Surgery)

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Specialties:

Dentistry

Address:

1289 E Hillsdale Blvd Suite 9, Foster City, CA 94404
(650)6389688 (Phone), (650)6389689 (Fax)

Languages:

English

Wen S Wu

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Specialties:

Family Medicine

Education:

Md, Taipei Medical College

Resumes

Wen Yi Wu

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Wen Hua Wu

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Wen Hsin Wu

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Wen Wu

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Wen Wu

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Wen Wu

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Wen Wu

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Clerk At Bnp Paribas

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Position:

clerk at BNP Paribas

Location:

United States

Industry:

Banking

Work:

BNP Paribas
clerk

Us Patents

Multistep Method Of Depositing Metal Seed Layers
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US Patent:

7682966, Mar 23, 2010
Filed:

Feb 1, 2007
Appl. No.:

11/701984
Inventors:

Robert Rozbicki - San Francisco CA, US
Bart van Schravendijk - Sunnyvale CA, US
Tom Mountsier - San Jose CA, US
Wen Wu - San Jose CA, US
Assignee:

Novellus Systems, Inc. - San Jose CA
International Classification:

H01L 23/535
US Classification:

438637, 438675, 438687, 257E21169, 257E21175
Abstract:

Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.

Compositionally Graded Titanium Nitride Film For Diffusion Barrier Applications
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US Patent:

7727882, Jun 1, 2010
Filed:

Dec 17, 2007
Appl. No.:

12/002780
Inventors:

Wen Wu - Milpitas CA, US
Chentao Yu - Sunnyvale CA, US
Girish Dixit - San Jose CA, US
Kenneth Jow - San Jose CA, US
Assignee:

Novellus Systems, Inc. - San Jose CA
International Classification:

H01L 21/4763
US Classification:

438627, 438625, 438643, 438656, 438675, 438685, 257E21584
Abstract:

A diffusion barrier film includes a layer of compositionally graded titanium nitride, having a nitrogen-rich portion and a nitrogen-poor portion. The nitrogen-rich portion has a composition of at least about 40% (atomic) N, and resides closer to the dielectric than the nitrogen-poor portion. The nitrogen-poor portion has a composition of less than about 30% (atomic) N (e. g. , between about 5-30% N) and resides in contact with the metal, e. g. , copper. The diffusion barrier film can also include a layer of titanium residing between the layer of dielectric and the layer of compositionally graded titanium nitride. The layer of titanium is often partially or completely converted to titanium oxide upon contact with a dielectric layer. The barrier film having a compositionally graded titanium nitride layer provides excellent diffusion barrier properties, exhibits good adhesion to copper, and reduces uncontrolled diffusion of titanium into interconnects.

Deposition Of Doped Copper Seed Layers Having Improved Reliability
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US Patent:

8017523, Sep 13, 2011
Filed:

May 16, 2008
Appl. No.:

12/122118
Inventors:

Hui-Jung Wu - Fremont CA, US
Daniel R. Juliano - Santa Clara CA, US
Wen Wu - San Jose CA, US
Girish Dixit - San Jose CA, US
Assignee:

Novellus Systems, Inc. - San Jose CA
International Classification:

H01L 21/4763
US Classification:

438687, 438627, 438675, 438678
Abstract:

Improved methods of depositing copper seed layers in copper interconnect structure fabrication processes are provided. Also provided are the resulting structures, which have improved electromigration performance and reduced line resistance. According to various embodiments, the methods involve depositing a copper seed bilayer on a barrier layer in a recessed feature on a partially fabricated semiconductor substrate. The bilayer has a copper alloy seed layer and a pure copper seed layer, with the pure copper seed layer is deposited on the copper alloy seed layer. The copper seed bilayers have reduced line resistance increase and better electromigration performance than conventional doped copper seed layers. Precise line resistance control is achieved by tuning the bilayer thickness to meet the desired electromigration performance.

Resistive Switching Memory Element Including Doped Silicon Electrode
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US Patent:

8183553, May 22, 2012
Filed:

Oct 29, 2009
Appl. No.:

12/608934
Inventors:

Prashant Phatak - San Jose CA, US
Tony Chiang - Campbell CA, US
Michael Miller - San Jose CA, US
Wen Wu - Pleasanton CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 47/00
US Classification:

257 4, 257E45003, 365148
Abstract:

A resistive switching memory element including a doped silicon electrode is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0. 1 and 1. 0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching and has a bandgap of greater than 4 eV, and the memory element switches from a low resistance state to a high resistance state and vice versa.

Nonvolatile Memory Element Including Resistive Switching Metal Oxide Layers
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US Patent:

8294219, Oct 23, 2012
Filed:

Jul 24, 2008
Appl. No.:

12/179538
Inventors:

Sandra G. Malhotra - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sean Barstow - San Jose CA, US
Tony Chiang - Campbell CA, US
Prashant B. Phatak - San Jose CA, US
Wen Wu - Pleasanton CA, US
Sunil Shanker - Santa Clara CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 21/02
US Classification:

257382, 257 68, 257296, 257 71, 257309, 257905, 257908, 257E27084, 257E27075, 257E27097, 257758, 257308
Abstract:

Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Charge Blocking Layers For Nonvolatile Memories
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US Patent:

8298890, Oct 30, 2012
Filed:

Sep 3, 2009
Appl. No.:

12/553918
Inventors:

Ronald John Kuse - Dublin CA, US
Monica Sawkar Mathur - San Jose CA, US
Wen Wu - Pleasanton CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 21/336
US Classification:

438257, 438211, 438593, 438972, 257239, 257261, 257298, 257E21179, 257E21495
Abstract:

A semiconductor memory element is described, including a substrate including a source region, a drain region, and a channel region, a tunnel oxide over the channel region of the substrate, a charge storage layer over the tunnel oxide, a charge blocking layer over the charge storage layer, and a control gate over the charge blocking layer. The charge blocking layer further includes a first layer including a transition metal oxide, a second layer including a metal silicate, a third layer including the transition metal oxide of the first layer.

Multistep Method Of Depositing Metal Seed Layers
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US Patent:

8298936, Oct 30, 2012
Filed:

Feb 3, 2010
Appl. No.:

12/699738
Inventors:

Robert Rozbicki - San Francisco CA, US
Bart van Schravendijk - Sunnyvale CA, US
Thomas Mountsier - San Jose CA, US
Wen Wu - Milpitas CA, US
Assignee:

Novellus Systems, Inc. - San Jose CA
International Classification:

H01L 21/283
H01L 21/67
US Classification:

438637, 438675, 438687, 257E21169, 257E21175
Abstract:

Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.

Nonvolatile Memory Elements
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US Patent:

8318573, Nov 27, 2012
Filed:

Dec 27, 2011
Appl. No.:

13/337611
Inventors:

Sandra G. Malhotra - San Jose CA, US
Pragati Kumar - Santa Clara CA, US
Sean Barstow - San Jose CA, US
Tony Chiang - Campbell CA, US
Prashant B. Phatak - San Jose CA, US
Wen Wu - Pleasanton CA, US
Sunil Shanker - Santa Clara CA, US
Assignee:

Intermolecular, Inc. - San Jose CA
International Classification:

H01L 21/02
US Classification:

438382, 257E21004, 257E27084, 257E27075, 257E27097, 257 68, 257296
Abstract:

Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.