Wen J Wu

US Patent:

7682966, Mar 23, 2010

Filed:

Feb 1, 2007

Appl. No.:

11/701984

Inventors:

Robert Rozbicki - San Francisco CA, US
Bart van Schravendijk - Sunnyvale CA, US
Tom Mountsier - San Jose CA, US
Wen Wu - San Jose CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 23/535

US Classification:

438637, 438675, 438687, 257E21169, 257E21175

Abstract:

Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.

US Patent:

8017523, Sep 13, 2011

Filed:

May 16, 2008

Appl. No.:

12/122118

Inventors:

Hui-Jung Wu - Fremont CA, US
Daniel R. Juliano - Santa Clara CA, US
Wen Wu - San Jose CA, US
Girish Dixit - San Jose CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/4763

US Classification:

438687, 438627, 438675, 438678

Abstract:

Improved methods of depositing copper seed layers in copper interconnect structure fabrication processes are provided. Also provided are the resulting structures, which have improved electromigration performance and reduced line resistance. According to various embodiments, the methods involve depositing a copper seed bilayer on a barrier layer in a recessed feature on a partially fabricated semiconductor substrate. The bilayer has a copper alloy seed layer and a pure copper seed layer, with the pure copper seed layer is deposited on the copper alloy seed layer. The copper seed bilayers have reduced line resistance increase and better electromigration performance than conventional doped copper seed layers. Precise line resistance control is achieved by tuning the bilayer thickness to meet the desired electromigration performance.

US Patent:

8298936, Oct 30, 2012

Filed:

Feb 3, 2010

Appl. No.:

12/699738

Inventors:

Robert Rozbicki - San Francisco CA, US
Bart van Schravendijk - Sunnyvale CA, US
Thomas Mountsier - San Jose CA, US
Wen Wu - Milpitas CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/283
H01L 21/67

US Classification:

438637, 438675, 438687, 257E21169, 257E21175

Abstract:

Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.