Wen Chin Yu

US Patent:

6927162, Aug 9, 2005

Filed:

Feb 23, 2004

Appl. No.:

10/782874

Inventors:

Wen Yu - Fremont CA, US
Jinsong Yin - Sunnyvale CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Paul Besser - Sunnyvale CA, US
Keizaburo Yoshie - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/4763
H01L021/44

US Classification:

438637, 438644, 438648, 438649, 438675

Abstract:

A method of forming a contact in a semiconductor device deposits a refractory metal contact layer in a contact hole on a conductive region portion in a silicon substrate. The refractory metal contact layer is reacted with the silicide region prior to a plasma treatment of a contact barrier metal layer formed within the contact hole. This prevents portions of the refractory metal contact layer from being nitridated prior to conversion to silicide.

US Patent:

7319065, Jan 15, 2008

Filed:

Aug 8, 2003

Appl. No.:

10/637406

Inventors:

Wen Yu - Fremont CA, US
Paul Raymond Besser - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/4763

US Classification:

438622, 438636, 438643, 438687

Abstract:

A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with a metal. The metal is planarized and a dielectric layer is formed over the contact layer. Via extension structures having the same aspect ratio as those in the contact layer are formed in the dielectric layer and aligned with the vias in the contact layer. The vias in the dielectric layer are filled with metal and the metal is planarized. The contact vias in the contact layer and the dielectric layer cooperate to form a composite via structure having the enhanced aspect ratio. Additional dielectric layers having via structures can be included in the composite contact structure to further enhance the aspect ratio of the via structure.

US Patent:

7407882, Aug 5, 2008

Filed:

Aug 27, 2004

Appl. No.:

10/928665

Inventors:

Connie Pin-Chin Wang - Menlo Park CA, US
Paul R. Besser - Sunnyvale CA, US
Wen Yu - Fremont CA, US
Jinsong Yin - Sunnyvale CA, US
Keizaburo Yoshie - Cupertino CA, US

Assignee:

Spansion LLC - Sunnyvale CA
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/4763

US Classification:

438649, 438655, 438683

Abstract:

A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion of the semiconductor substrate. Titanium silicide is disposed on the dielectric layer, sidewalls, and the exposed portion of the semiconductor substrate. The titanium silicide may be formed by disposing titanium on the dielectric layer, sidewalls, and exposed portion of the semiconductor substrate and reacting the titanium with silane. Alternatively, the titanium silicide may be sputter deposited. A layer of titanium nitride is formed on the titanium silicide. A layer of tungsten is formed on the titanium nitride. The tungsten, titanium nitride, and titanium silicide are polished to form the contact structures.

US Patent:

20080146028, Jun 19, 2008

Filed:

Dec 19, 2006

Appl. No.:

11/641647

Inventors:

Wen Yu - Fremont CA, US
Stephen B. Robie - Cupertino CA, US
Jeremias D. Romero - Hayward CA, US

International Classification:

H01L 21/44

US Classification:

438656, 257E21476

Abstract:

The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50 C. or less, with the deposition taking place at a power level of 300 W or less.

US Patent:

20090278173, Nov 12, 2009

Filed:

May 6, 2008

Appl. No.:

12/116200

Inventors:

Shenqing FANG - Fremont CA, US
Connie WANG - Mountain View CA, US
Wen YU - Fremont CA, US
Fei WANG - San Jose CA, US

International Classification:

H01L 29/66
H01L 21/4763

US Classification:

257211, 438622, 257E29166, 257E21495

Abstract:

An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

US Patent:

53961650, Mar 7, 1995

Filed:

Feb 2, 1993

Appl. No.:

8/013809

Inventors:

Jeffrey H. Hwang - Saratoga CA
Peter Reischl - Los Gatos CA
Wen H. Yu - San Francisco CA
Kartik Bhatt - Newark CA
Gary J. Lin - Campbell CA
George C. Chen - Milpitas CA

Assignee:

Teledyne Industries, Inc. - Mountain View CA

International Classification:

G05F 170

US Classification:

323210

Abstract:

A power transfer method and apparatus for efficient transfer of power are disclosed. Input power is converted in an essentially lossless manner to an intermediate form having a voltage or current in excess of that desired at the load. The intermediate power form is split into first and second parts, where the first part of the intermediate power form approximately matches an output power form desired at an output of the power transfer apparatus and the second part represents an excess power form. The first part of the intermediate power form is transferred to the output of the power transfer apparatus and the excess part is stored. Part or all of the stored excess energy is recycled in an essentially lossless manner, converted into a form that approximately matches the output power form desired at the output of the power transfer apparatus and transferred to the output of the power transfer apparatus.

US Patent:

20190198716, Jun 27, 2019

Filed:

Dec 19, 2018

Appl. No.:

16/226609

Inventors:

- San Jose CA, US
Oleg SHCHEKIN - San Francisco CA, US
Ashish TANDON - Sunnyvale CA, US
Rajat SHARMA - San Jose CA, US
Joseph FLEMISH - Palo Alto CA, US
Andrei PAPOU - San Jose CA, US
Wen YU - Pleasanton CA, US
Erik YOUNG - San Jose CA, US

Assignee:

Lumileds LLC - San Jose CA

International Classification:

H01L 33/46
H01L 33/50
H01L 33/60
H01L 33/10
H01L 27/15

Abstract:

A light-emitting device is disclosed which includes a segmented active layer disposed between a segmented conductivity layer and a continuous conductivity layer, the active layer, the segmented conductivity layer, and the continuous conductivity layer being arranged to define a plurality of pixels, each pixel including a different segment of the segmented conductivity layer and the segmented active layer. A continuous wavelength converting layer disposed on the continuous conductivity layer is provided. A plurality of first contacts, each first contact being electrically connected to a different segment of the segmented conductivity layer is provided. One or more second contacts that are electrically connected to the continuous conductivity layer are also provided, the number of second contacts being less than the number of first contacts.

US Patent:

20190189682, Jun 20, 2019

Filed:

Dec 19, 2018

Appl. No.:

16/226239

Inventors:

- San Jose CA, US
Joseph Robert FLEMISH - Palo Alto CA, US
Ashish TANDON - Sunnyvale CA, US
Rajat SHARMA - San Jose CA, US
Andrei PAPOU - San Jose CA, US
Wen YU - Pleasanton CA, US
Yu-Chen SHEN - Sunnyvale CA, US
Luke GORDON - Santa Barbara CA, US

Assignee:

Lumileds LLC - San Jose CA

International Classification:

H01L 27/15
H01L 33/32
H01L 33/50
H01L 33/60
H01L 33/62
H01L 33/00
F21S 41/153

Abstract:

A light emitting diode (LED) array may include an epitaxial layer comprising a first pixel and a second pixel separated by an isolation region. A reflective layer may be formed on the epitaxial layer. A p-type contact layer may be formed on the reflective layer. The isolation region may have a width that is at least a width of a trench formed in a p-type contact layer.