Wen Jun Yu

US Patent:

6927162, Aug 9, 2005

Filed:

Feb 23, 2004

Appl. No.:

10/782874

Inventors:

Wen Yu - Fremont CA, US
Jinsong Yin - Sunnyvale CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Paul Besser - Sunnyvale CA, US
Keizaburo Yoshie - Cupertino CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L021/4763
H01L021/44

US Classification:

438637, 438644, 438648, 438649, 438675

Abstract:

A method of forming a contact in a semiconductor device deposits a refractory metal contact layer in a contact hole on a conductive region portion in a silicon substrate. The refractory metal contact layer is reacted with the silicide region prior to a plasma treatment of a contact barrier metal layer formed within the contact hole. This prevents portions of the refractory metal contact layer from being nitridated prior to conversion to silicide.

US Patent:

7306988, Dec 11, 2007

Filed:

Feb 22, 2005

Appl. No.:

11/063138

Inventors:

Steven C. Avanzino - Cupertino CA, US
Wen Yu - Fremont CA, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX
Spansion LLC - Sunnyvale CA

International Classification:

H01L 21/8242

US Classification:

438252, 438687, 438387, 257 40, 257301, 257 43, 257E2166

Abstract:

Methods of making memory devices/cells are disclosed. A memory cell contains first and second electrode layers and a controllably conductive media therebetween. The controllably conductive media contains a copper sulfide-containing passive layer and active layer containing a Cu-doped tantalum oxide and/or titanium oxide layer. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.

US Patent:

7319065, Jan 15, 2008

Filed:

Aug 8, 2003

Appl. No.:

10/637406

Inventors:

Wen Yu - Fremont CA, US
Paul Raymond Besser - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/4763

US Classification:

438622, 438636, 438643, 438687

Abstract:

A semiconductor component having a composite via structure with an enhanced aspect ratio and a method for manufacturing the semiconductor component. Vias having a first aspect ratio are formed in a contact layer disposed on a semiconductor substrate and filled with a metal. The metal is planarized and a dielectric layer is formed over the contact layer. Via extension structures having the same aspect ratio as those in the contact layer are formed in the dielectric layer and aligned with the vias in the contact layer. The vias in the dielectric layer are filled with metal and the metal is planarized. The contact vias in the contact layer and the dielectric layer cooperate to form a composite via structure having the enhanced aspect ratio. Additional dielectric layers having via structures can be included in the composite contact structure to further enhance the aspect ratio of the via structure.

US Patent:

7407882, Aug 5, 2008

Filed:

Aug 27, 2004

Appl. No.:

10/928665

Inventors:

Connie Pin-Chin Wang - Menlo Park CA, US
Paul R. Besser - Sunnyvale CA, US
Wen Yu - Fremont CA, US
Jinsong Yin - Sunnyvale CA, US
Keizaburo Yoshie - Cupertino CA, US

Assignee:

Spansion LLC - Sunnyvale CA
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/4763

US Classification:

438649, 438655, 438683

Abstract:

A semiconductor component having a titanium silicide contact structure and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate. An opening having sidewalls is formed in the dielectric layer and exposes a portion of the semiconductor substrate. Titanium silicide is disposed on the dielectric layer, sidewalls, and the exposed portion of the semiconductor substrate. The titanium silicide may be formed by disposing titanium on the dielectric layer, sidewalls, and exposed portion of the semiconductor substrate and reacting the titanium with silane. Alternatively, the titanium silicide may be sputter deposited. A layer of titanium nitride is formed on the titanium silicide. A layer of tungsten is formed on the titanium nitride. The tungsten, titanium nitride, and titanium silicide are polished to form the contact structures.

US Patent:

7468296, Dec 23, 2008

Filed:

Nov 30, 2005

Appl. No.:

11/290787

Inventors:

Ercan Adem - Sunnyvale CA, US
Matthew Buynoski - Palo Alto CA, US
Robert Chiu - San Jose CA, US
Bryan Choo - Mountain View CA, US
Calvin Gabriel - Cupertino CA, US
Joong Jeon - Cupertino CA, US
David Matsumoto - San Jose CA, US
Jeffrey Shields - Sunnyvale CA, US
Bhanwar Singh - Morgan Hill CA, US
Winny Stockwell - Redwood City CA, US
Wen Yu - Fremont CA, US

Assignee:

Spansion LLC - Sunnyvale CA
Advanced Micro Devices Inc. - Sunnyvale CA

International Classification:

H01L 21/8234
H01L 27/10

US Classification:

438237, 438328, 438600, 257202, 257208

Abstract:

In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

US Patent:

8039391, Oct 18, 2011

Filed:

Mar 27, 2006

Appl. No.:

11/388976

Inventors:

Jinsong Yin - Sunnyvale CA, US
Wen Yu - Fremont CA, US
Connie Pin-Chin Wang - Menlo Park CA, US
Paul Besser - Sunnyvale CA, US
Keizaburo Yoshie - Cupertino CA, US

Assignee:

Spansion LLC - Sunnyvale CA
Globalfoundries Inc. - Grand Cayman

International Classification:

H01L 21/44

US Classification:

438656, 438664, 257757, 257E29111

Abstract:

A method of forming a contact in a semiconductor device provides a titanium contact layer in a contact hole and a MOCVD-TiN barrier metal layer on the titanium contact layer. Impurities are removed from the MOCVD-TiN barrier metal layer by a plasma treatment in a nitrogen-hydrogen plasma. The time period for plasma treating the titanium nitride layer is controlled so that penetration of nitrogen into the underlying titanium contact layer is substantially prevented, preserving the titanium contact layer for subsequently forming a titanium silicide at the bottom of the contact.

US Patent:

20080146028, Jun 19, 2008

Filed:

Dec 19, 2006

Appl. No.:

11/641647

Inventors:

Wen Yu - Fremont CA, US
Stephen B. Robie - Cupertino CA, US
Jeremias D. Romero - Hayward CA, US

International Classification:

H01L 21/44

US Classification:

438656, 257E21476

Abstract:

The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50 C. or less, with the deposition taking place at a power level of 300 W or less.

US Patent:

20090278173, Nov 12, 2009

Filed:

May 6, 2008

Appl. No.:

12/116200

Inventors:

Shenqing FANG - Fremont CA, US
Connie WANG - Mountain View CA, US
Wen YU - Fremont CA, US
Fei WANG - San Jose CA, US

International Classification:

H01L 29/66
H01L 21/4763

US Classification:

257211, 438622, 257E29166, 257E21495

Abstract:

An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.