Wesley D Hardell

US Patent:

6986141, Jan 10, 2006

Filed:

Dec 17, 1998

Appl. No.:

09/213970

Inventors:

Wilhelmus J. M. Diepstraten - Haghorst, NL
Michael A. Fischer - San Antonio TX, US
Wesley D. Hardell - San Antonio TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 4/46
G06F 15/00

US Classification:

718108, 712228

Abstract:

A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) a time slice instruction counter that counts a number of instructions executed with respect to a given background task and (2) a background task controller that cyclicly executes a context corresponding to another background task when the number of instructions executed equals a dynamically-programmable time slice value.

US Patent:

7444641, Oct 28, 2008

Filed:

Dec 17, 1998

Appl. No.:

09/213984

Inventors:

Wilhelmus J. M. Diepstraten - Haghorst, NL
Michael A. Fischer - San Antonio TX, US
Wesley D. Hardell - San Antonio TX, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G06F 15/00
G06F 9/46

US Classification:

718107, 712228

Abstract:

A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) an event recorder that records occurrences of predetermined events and (2) an event acknowledger, associated with the event recorder, that acknowledges ones of the events based on an identity of a currently-active context.

US Patent:

20020089994, Jul 11, 2002

Filed:

May 4, 2001

Appl. No.:

09/849002

Inventors:

Wesley Hardell - San Antonio TX, US
Michael Fischer - San Antonio TX, US

International Classification:

H04L012/28

US Classification:

370/412000, 370/392000

Abstract:

A communications system including a scheduling entity and a transceiver coupled across a variable timing interface. The scheduling entity forwards frames for transmission and identifies selected frames as persistent. The transceiver includes a queue, a frame manager and a transmission scheduler. The frame manager receives and enqueues forwarded frames and the transmission scheduler dequeues and transmits frames from the queue and forwards persistent frames back to the frame manager. The transmission scheduler includes persistence logic that detects a persistent mark and asserts a persistent signal that is detected by the transmission scheduler. The scheduling entity identifies a persistent frame by setting a bit in a transmit control field of the frame descriptor. The scheduling entity sends a clear persistence command to the transceiver to clear a persistent mark of an identified frame. The transceiver may be configured for wireless communications.

US Patent:

20090240928, Sep 24, 2009

Filed:

Mar 18, 2008

Appl. No.:

12/050622

Inventors:

Michael A. Fischer - San Antonio TX, US
Wesley D. Hardell - San Antonio TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G06F 9/30

US Classification:

712226, 712E09016

Abstract:

Extended, alternate and/or modified instruction behavior can be established using a program construct that appears outside a bounded block of program code in such a way that the behavioral changes are limited to the bounded block and coincide with a particular point in the execution thereof. These extensions, alternations and/or modifications are supported in some processor embodiments in ways that add neither additional code space nor additional execution cycles to the bounded block. In general, the particular point in execution of the bounded block may be specified in a variety of ways, including positionally or temporally. Techniques described herein have broad applicability, but will be understood by persons of ordinary skill in the art in the context of certain illustrative code blocks, including zero- (or low-) overhead loops, lightweight procedures and very long instruction word (VLIW) type instruction packets, and processors that support them.

US Patent:

62437364, Jun 5, 2001

Filed:

Dec 17, 1998

Appl. No.:

9/215067

Inventors:

Wilhelmus J. M. Diepstraten - Haghorst, NL
Michael A. Fischer - San Antonio TX
Wesley D. Hardell - San Antonio TX

Assignee:

Agere Systems Guardian Corp. - Murray Hill NJ

International Classification:

G06F 946
G06F 900
G06F 738

US Classification:

709108

Abstract:

A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) memory that contains contexts corresponding to background tasks to be executed in the processor, the contexts having status indicators associated therewith and (2) a background task controller that reads the status indicators associated with the contexts and cyclicly activates the contexts based on the status indicators.

US Patent:

62054686, Mar 20, 2001

Filed:

Dec 17, 1998

Appl. No.:

9/213618

Inventors:

Wilhelmus J. M. Diepstraten - Haghorst, NL
Michael A. Fischer - San Antonio TX
Wesley D. Hardell - San Antonio TX

Assignee:

Lucent Technologies, Inc. - Murray Hill NJ

International Classification:

G06F 900

US Classification:

709108

Abstract:

A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) an event recorder that records occurrences of events and (2) an encoder, associated with the event recorder, that, in response to a software instruction, priority encodes bits corresponding to at least some of the events to generate therefrom an event-dependent vector to allow the processor to branch as a function thereof. Vectoring is per-instance of the vector decode software instruction, not per-event or per-context.

US Patent:

62601504, Jul 10, 2001

Filed:

Dec 17, 1998

Appl. No.:

9/213102

Inventors:

Wilhelmus J. M. Diepstraten - Haghorst, NL
Michael A. Fischer - San Antonio TX
Wesley D. Hardell - San Antonio TX

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

G06F 132

US Classification:

713323

Abstract:

A context controller for managing multitasking in a processor and a method of operating the same. In one embodiment, the context controller includes: (1) foreground and background task controllers that allocate processor resources to active contexts corresponding to foreground and background tasks, respectively, and (2) mode switching circuitry, coupled to the foreground and background task controllers, that places the processor in an idle state and a power saving mode when all of the contexts are inactive.