Wesley Wai Lee

US Patent:

55947026, Jan 14, 1997

Filed:

Jun 28, 1995

Appl. No.:

8/495867

Inventors:

Larry N. Wakeman - Mountain View CA
Roy T. Myers - Santa Clara CA
Wesley C. Lee - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G11C 800
G06F 1500
H01J 300

US Classification:

36523005

Abstract:

A multi-first-in-first-out (henceforth "multi-FIFO") memory circuit in accordance with this invention comprises: (1) a plurality of groups of storage elements, for example, each group corresponds to a first-in-first-out (FIFO) memory (2) a time multiplexed first address generator for generating address signals of a storage element from a first group that is cyclically selected from the plurality of groups by a sequencer included in the first address generator and (3) a second address generator for generating address signals of a number of successive storage elements from a second group that is selected from the plurality of groups by a signal on a group request terminal of the second address generator. In one embodiment the storage elements are part of a dualport random-access-memory (RAM), and are accessed by each of the first and second address generators using a number of pairs of pointer registers that are coupled to the address generators. Each pair of pointer registers includes a read pointer register that indicates a corresponding group's next storage element to be read and a write pointer register that indicates the group's next storage element to be written.

US Patent:

54992427, Mar 12, 1996

Filed:

Jan 31, 1995

Appl. No.:

8/381183

Inventors:

Wesley Lee - San Jose CA
Jerry Grand - Atlanta GA

Assignee:

National Semiconductor Corporation - DE

International Classification:

H04L 12413

US Classification:

370 853

Abstract:

N bit-collision circuits of a collision detection circuit each include a bit-collision circuit driver connected to drive an x-th line of the common collision detection bus if the x-th line of the station's corresponding identifier signal is at a low level. The bits of the identifier signal are only provided to the bit-collision circuit drivers while an enable signal is asserted. The driver has an open-collector-type connection to the x-th line of the common collision detection bus. That is, the bit-collision circuit driver, when not driving, presents a high impedance at its output. Each bit-collision circuit further includes an XOR device for use in comparing the level of the x-th line of the collision bus with the level of the x-th bit of the station's identifier signal. A NOR device is for combining receives the comparison results from the XOR devices of the bit-collision circuits and provides a combined bit-collision result. A global collision indication line driver has an open-collector-type output interface to a global collision indication line.