William P Cornwell

US Patent:

7307447, Dec 11, 2007

Filed:

Oct 27, 2005

Appl. No.:

11/263138

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Todd M. Rasmus - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16
H03B 1/00

US Classification:

326 30, 326 27, 327108, 327112

Abstract:

A circuit design method and transmitter that enables flexible control of amplitude, pre-emphasis, and slew rate utilizing a design of a segmented self-series terminated (SSST) transmitter having a parallel configuration of multiple, individually controllable segments of dual pull-up and pull-down transistors. Amplitude control, slew rate control and pre-emphasis control are enabled by manipulation/selection of normal or inverted inputs for the various segments. Also provided is a mechanism for providing/maintaining accurate output across a self-series terminated (SST) transmitter by regulating the supply voltage. Regulation of the supply voltage allows compatibility with conventional serial link receiver termination voltages and protects the transmitter output devices when those voltages are larger than the normal supply for the devices.

US Patent:

7368902, May 6, 2008

Filed:

Oct 28, 2005

Appl. No.:

11/262101

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Vernon R. Norman - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 35/00
H03K 19/003
G06F 19/00

US Classification:

3241581, 324601, 326 30, 363 95, 702107

Abstract:

Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

US Patent:

7570071, Aug 4, 2009

Filed:

Feb 8, 2008

Appl. No.:

12/028451

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Vernon R. Norman - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G01R 35/00
H03K 19/003
G06F 19/00

US Classification:

324765, 324601, 326 30, 702107

Abstract:

Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

US Patent:

7698802, Apr 20, 2010

Filed:

Feb 8, 2008

Appl. No.:

12/028439

Inventors:

Steven M. Clements - Raleigh NC, US
William P. Cornwell - Durham NC, US
Carrie E. Cox - Cary NC, US
Vernon R. Norman - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28

US Classification:

29593, 29832, 29842, 29846, 29854, 3241581, 324601, 326 30, 363 95, 702107

Abstract:

A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.