William F Desjardin

US Patent:

6693671, Feb 17, 2004

Filed:

Mar 22, 2000

Appl. No.:

09/533051

Inventors:

Eric G. Stevens - Rochester NY
William F. Desjardin - Holley NY

Assignee:

Eastman Kodak Company - Rochester NY

International Classification:

H04N 5335

US Classification:

348314, 348315, 348299

Abstract:

A structure for a fast-dump gate for charge coupled devices that does not require a separate contact to a drain region instead using the existing drain of a lateral overflow drain (LOD) typically used for antiblooming purposes. LOD structures are typically used on full-frame CCD image sensors. By using the LOD as the drain for a fast-dump gate, a separate opening in the gate electrode for the drain contact is avoided, thereby making the structure more compact. Gate control is provided by etching a hole in the CCD gate electrode over the overflow channel region of the LOD structure, and overlaying this with one of the subsequent gate electrode layers. This subsequent gate electrode is then used to control the fast-dump operation. Timing is shown for a two-phase CCD being operated with accumulation-mode clocking. Other types of CCDs and clocking schemes may be used.

US Patent:

7304676, Dec 4, 2007

Filed:

Aug 6, 2003

Appl. No.:

10/635332

Inventors:

John T. Compton - Leroy NY, US
David M. Charneski - Hilton NY, US
Wayne W. Hintz - Bergen NY, US
Edward P. Lawler - Fairport NY, US
William F. DesJardin - Holley NY, US
Richard B. Brolly - Fairport NY, US
Herbert J. Erhardt - Webster NY, US

Assignee:

Eastman Kodak Company - Rochester NY

International Classification:

H04N 5/335

US Classification:

348312

Abstract:

A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.

US Patent:

7402882, Jul 22, 2008

Filed:

Aug 23, 2004

Appl. No.:

10/924061

Inventors:

Shen Wang - Webster NY, US
William F. DesJardin - Holley NY, US
Robert P. Fabinski - Rochester NY, US
David N. Nichols - Fairport NY, US
Christopher Parks - Rochester NY, US
Eric G. Stevens - Webster NY, US

Assignee:

Eastman Kodak Company - Rochester NY

International Classification:

H01L 29/72

US Classification:

257435, 257 81, 257 99, 257223, 257225, 257230, 257294

Abstract:

A charge coupled device includes a substrate; a plurality of image pixels arranged in a two dimensional array in the substrate for capturing an electronic representation of an image and for transferring charge in a first direction; a transfer mechanism for transferring charge in a second direction from the plurality of the image pixels for further processing; an amplifier structure disposed in the substrate that receives the charge from the transfer mechanism and converts the charge into a voltage signal; a first opaque layer spanning over the amplifier for blocking near-infrared light inherently generated by an electrical field within the amplifier structure when a voltage is applied; and a second opaque layer deposited into the substrate for also blocking near-infrared light inherently generated by an electrical field within the amplifier structure when a voltage is applied.

US Patent:

54480892, Sep 5, 1995

Filed:

Mar 29, 1994

Appl. No.:

8/219758

Inventors:

Edmund K. Banghart - Pittsford NY
Edward T. Nelson - Pittsford NY
William F. DesJardin - Rochester NY
James P. Lavine - Rochester NY
Bruce C. Burkey - Rochester NY

Assignee:

Eastman Kodak Company - Rochester NY

International Classification:

H01L 2978
H01L 3100
H01L 2714

US Classification:

257222

Abstract:

A charge-coupled device having an improved charge-transfer efficiency over a broad temperature range. The device comprises a substrate of semiconductor material of one conductivity type; a first buried channel formed in the substrate and of a conductivity type opposite to that of the substrate; a second buried channel of a conductivity type opposite to that of the substrate formed in the same region of the substrate as the first buried channel and having a greater depth of penetration into the substrate than the first buried channel; compensated regions formed at intervals in the buried channels providing a means for containing individual packets of charge and shaped for inducing a narrow channel effect and for producing a fringing electric field in a direction of charge transfer in uncompensated buried channel regions; electrode gates associated with each pair of adjoining compensated and uncompensated regions in the device; and means for clocking the electrodes for causing a string of charge packets to be transferred through the device.

US Patent:

53492340, Sep 20, 1994

Filed:

May 29, 1992

Appl. No.:

7/890451

Inventors:

William F. DesJardin - Rochester NY
Edward J. Ozimek - Penfield NY
Luis A. Rivera - Rochester NY
Terry Tarn - Pittsford NY

Assignee:

Eastman Kodak Company - Rochester NY

International Classification:

H01L 2302
H01L 2144

US Classification:

257684

Abstract:

Apparatus and a method for the packaging of semiconductor chips to simplify assembly while improving thermal dissipation from the chip and reducing stress in the chip due to differential thermal expansion between the chip and its package as they are cycled over a temperature range are disclosed. An adhesive tape covers an active area of the chip and leaving bonding pads on the chip exposed through a recess in the adhesive tape. A body with a similar recess supports the other side of the tape. Wire bonds are made in the recess to connect bonding pads on the body to the chip. A lid covers the recess to protect the wire bonds.