William G George

US Patent:

39382419, Feb 17, 1976

Filed:

Jun 24, 1974

Appl. No.:

5/482528

Inventors:

William Lloyd George - Scottsdale AZ
Robert Guy Hays - Scottsdale AZ
Chongkook John Rhee - Scottsdale AZ

Assignee:

Motorola, Inc. - Chicago IL

International Classification:

B01J 1700

US Classification:

29571

Abstract:

The disclosed junction field-effect transistor (FET) has a precisely controlled gate configuration which enables either high power operation or high frequency operation or both. The FET is manufactured by steps including the growing of a first epitaxial layer having a predetermined crystallographic orientation on a substrate to form a drain. Next, a first anisotropic etch of the epitaxial layer provides "U"-shaped grooves with flat bottoms, therein through which a gate is diffused having internal side walls of uniform depth that define the source-to-drain channel. A second epitaxial layer is then grown on the surface of the first epitaxial layer and of the gate to provide a source. A second anisotropic etch exposes a portion of the gate, which also forms an etch stop, to facilitate electrical contact thereto. Current flowing through the channel is controlled in response to an input signal applied between the gate and source which adjusts the thickness of a depletion region extending into the channel.

US Patent:

40873145, May 2, 1978

Filed:

Sep 13, 1976

Appl. No.:

5/723006

Inventors:

William L. George - Scottsdale AZ
Richard W. Wilson - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

C23F 102

US Classification:

156643

Abstract:

A metallization system and process for forming bonding pedestals suitable for subsequent gang-bonding of multileaded semiconductor devices. The metallurgical components are selected for corrosion resistance and permit the use of selective etchants for yield enhancement.