William Kyle Greer

US Patent:

58840940, Mar 16, 1999

Filed:

Apr 2, 1998

Appl. No.:

/053986

Inventors:

Ralph Murray Begun - Raleigh NC
William Robert Greer - Waterville VT
Christopher Michael Herring - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1314

US Classification:

395830

Abstract:

A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus. Logic is provided to detect during the first ROM CPU cycle whether the ROM is on the peripheral bus or on the local bus, and the MC/PBHB will then either pass the signal to the peripheral bus if that is where the ROM is located, or will not pass it--in which case the local bus controller will take over and read the ROM which must be located on the local bus since it is not located on the peripheral bus.

US Patent:

56805560, Oct 21, 1997

Filed:

Sep 3, 1996

Appl. No.:

8/706934

Inventors:

Ralph Murray Begun - Raleigh NC
William Robert Greer - Waterville VT
Christopher Michael Herring - Essex Junction VT

Assignee:

International Business Machines Corporation - Armond NY

International Classification:

G06F 1300

US Classification:

395311

Abstract:

A personal computer system is provided which includes a CPU, with the CPU being operable by a BIOS including initialization or booting instructions. The system includes a local bus and a peripheral bus. A bus interface chip, including a memory controller/peripheral bus host bridge (MC/PBHB) interconnects the local bus and the peripheral bus, and includes a latch which includes as its input clock cycles generated by the CPU. The initialization instructions of the BIOS are contained in a non-volatile ROM module located to write onto either the local bus or the peripheral bus. The MC/PBHB unit is able to decode and handle ROM cycles and is configured to either pass or not pass ROM read cycles depending upon certain control states that identify whether the ROM is located on the local bus or the peripheral bus. Logic is provided to detect during the first ROM CPU cycle whether the ROM is on the peripheral bus or on the local bus, and the MC/PBHB will then either pass the signal to the peripheral bus if that is where the ROM is located, or will not pass it--in which case the local bus controller will take over and read the ROM which must be located on the local bus since it is not located on the peripheral bus.