William D Higdon

US Patent:

6375062, Apr 23, 2002

Filed:

Nov 6, 2000

Appl. No.:

09/706543

Inventors:

William D. Higdon - Greentown IN
Frank Stepniak - Noblesville IN

Assignee:

Delphi Technologies, Inc. - Troy MI

International Classification:

B23K 3102

US Classification:

228214, 22818022

Abstract:

A solder bumping method and structure for fine solder bump pitches. The method makes use of a semiconductor device having an input/output pad whose surface is provided with a solderable metal layer that serves as the UBM of the solder bump. A sacrificial layer is formed on the surface of the device to surround the metal layer. A plating seed layer is then formed on the metal layer and the surrounding surface of the sacrificial layer, after which a mask is formed on the seed layer and a via is defined in the mask to expose portions of the seed layer overlying the metal layer and the sacrificial layer. A solder material is deposited on the seed layer exposed within the via. The mask is then removed, followed by removal of a portion of the seed layer that is not covered by the solder material, leaving intact that portion of the seed layer beneath the solder material. The sacrificial layer is then removed, including that portion of the sacrificial layer underlying the seed layer, such that a gap is formed between the substrate and the remaining seed layer. Finally, the solder material is reflowed to form a solder bump into which the remaining seed layer is dissolved.

US Patent:

6822327, Nov 23, 2004

Filed:

Jun 13, 2003

Appl. No.:

10/461318

Inventors:

Pankaj Mithal - Kokomo IN
William D. Higdon - Greentown IN
Mark W. Gose - Kokomo IN
John M. Dikeman - Kokomo IN
Frank Stepniak - Noblesville IN

Assignee:

Delphi Technologies, Inc. - Troy MI

International Classification:

H01L 2940

US Classification:

257734, 257773, 257782, 257786

Abstract:

A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.

US Patent:

20050046024, Mar 3, 2005

Filed:

Oct 8, 2004

Appl. No.:

10/961446

Inventors:

Pankaj Mithal - Kokomo IN, US
William Higdon - Greentown IN, US
Mark Gose - Kokomo IN, US
John Dikeman - Kokomo IN, US
Frank Stepniak - Noblesville IN, US

International Classification:

H01L021/44

US Classification:

257734000

Abstract:

A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.

US Patent:

20070029669, Feb 8, 2007

Filed:

Aug 5, 2005

Appl. No.:

11/198419

Inventors:

Frank Stepniak - Noblesville IN, US
William Higdon - Greentown IN, US

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257734000

Abstract:

An integrated circuit (IC) includes a semiconductor material, electronic circuitry formed on the semiconductor material, a contact layer formed on the electronic circuitry, a final passivation layer formed on the contact layer and an under-bump metallurgy (UBM) formed on at least a portion of the final passivation layer. The contact layer includes a plurality of contacts pads for providing external access to the electronic circuitry. The final passivation layer includes a plurality of windows that extend through the final passivation layer to the contact pads. The UBM includes an aluminum layer having a thickness of about 800 angstroms to about 1200 angstroms, a nickel/vanadium (Ni/V) layer having a thickness of about 800 angstroms to about 1200 angstroms and a copper (Cu) layer having a thickness of about 800 angstroms to about 1200 angstroms.

US Patent:

55477402, Aug 20, 1996

Filed:

Mar 23, 1995

Appl. No.:

8/408792

Inventors:

William D. Higdon - Greentown IN
Susan A. Mack - Kokomo IN
Ralph E. Cornell - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

B32B 900

US Classification:

428209

Abstract:

A flip chip integrated circuit device (110) is provided having a surface, a perimeter, and solder bumps (112) located on the surface. At least one solder bump (112), and preferably a plurality of solder bumps (112), are spaced apart from the perimeter of the device (110). Electrically conductive runners (118) extend from the perimeter of the device (110) to each of those solder bumps (112) that are spaced apart from the perimeter, so as to electrically interconnect the solder bumps (112) to a point, such as a pad (116), at the perimeter. As a result, not all of the solder bumps (112) employed by the device (110) need be accommodated at the perimeter of the device (110), such that the size and number of the solder bumps (112) does not dictate the size of the device (110).

US Patent:

44006810, Aug 23, 1983

Filed:

Feb 23, 1981

Appl. No.:

6/237474

Inventors:

Ronald E. Brown - Kokomo IN
Lamonte R. Edison - Kokomo IN
William D. Higdon - Greentown IN

Assignee:

General Motors Corporation - Detroit MI

International Classification:

G01L 122

US Classification:

338 4

Abstract:

A diaphragm is formed in a silicon chip by etching a rectangular cavity in one side thereof and piezoresistive resistors are formed in the other surface of the chip to sense stress changes on the diaphragm due to pressure changes. At least one resistor is placed along the edge of the diaphragm where a sharp stress peak occurs. To avoid the problem of inaccurate placement of the resistor relative to the peak, the resistor is slanted with respect to the stress ridge at a small angle of 10. degree. to 20. degree. This makes the resistor placement and cavity alignment much less critical thereby assuring greater uniformity of response from one sensor to another at the expense of signal size for a given pressure change on the device.

US Patent:

56070993, Mar 4, 1997

Filed:

Apr 24, 1995

Appl. No.:

8/426861

Inventors:

Shing Yeh - Buffalo Grove IL
William D. Higdon - Greentown IN
Ralph E. Cornell - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

H01L 2144

US Classification:

22818022

Abstract:

A carrier device (10) is provided for transferring solder bumps (16) to a surface of a flip chip integrated circuit device (18). The carrier device (10) is equipped with cavities (12) on its surface for receiving and retaining solder material (14), by which the solder material (14) can be transferred to the flip chip (18) as molten solder bumps (16). The cavities (12) are located on the surface of the carrier device (10) such that the location of the solder material (14) will correspond to the desired solder bump locations on the flip chip (18) when the carrier device (10) is registered with the flip chip (18). The size of the cavities (12) can be controlled in order to deliver a precise quantity of solder material (14) to the flip chip (18).

US Patent:

51152452, May 19, 1992

Filed:

Sep 4, 1990

Appl. No.:

7/576915

Inventors:

Cheng P. Wen - Mission Viejo CA
Gregory S. Mendolia - Torrance CA
Mario Siracusa - Fountain Valley CA
Joseph J. Maieron - Kokomo IN
William D. Higdon - Greentown IN
John J. Wooldridge - Manhattan Beach CA
Jon Gulick - Hawthrone CA

Assignee:

Hughes Aircraft Company - Los Angeles CA
Delco Electronics Corporation - Kokomo IN

International Classification:

H01Q 1326

US Classification:

342175

Abstract:

A microwave radar transceiver assembly (30) includes a monolithic microwave integrated circuit (MMIC) chip (58) having a coplanar waveguide transmssion lines (100, 102, 104) formed on the same surface (58a) as the electronic elements thereof. Coplanar waveguide transmission lines (68, 70, 72) are also formed on a surface (62a) of a substrate (62). The transceiver chip (58), in addition to other chips (56, 60), are mounted on the substrate (62) in a flip-chip arrangement, with the respective surfaces (58a, 62a) on which the transmission lines (100, 102, 104; 68, 70, 72) are formed facing each other. Electrically conductive bumps (106, 108, 110) are formed on portions of the transmission lines (100, 102, 104) of the chips (56, 58, 60) which are to be interconneced with the transmission lines (68, 70, 72) of the substrate (62), and solder (114) is formed on the portions of the transmission line (68, 70, 72) of the substrate (62) which are to be interconnected with the transmission lines (100, 102, 104) of the chips (56, 68, 60). The bumps (106, 108, 110) provide spacing between the mating surfaces (58a, 62a) of the substrate (62) and chips (56, 68, 60), and isolation between electronic elements on the chips (56, 58, 60).