William R Huff

US Patent:

6833767, Dec 21, 2004

Filed:

Jun 26, 2003

Appl. No.:

10/606682

Inventors:

William J. Huff - La Jolla CA
Lawrence J. Malone - Carlsbad CA
Daniel R. Meacham - Del Mar CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L 300

US Classification:

331 17, 332128, 331 23

Abstract:

A method includes identifying a setting for a capacitor bank associated with a voltage-controlled oscillator in a closed-loop phase-locked-loop. The setting represents a combination of one or more capacitors in the capacitor bank. The method also includes estimating a gain introduced by the closed-loop phase-locked-loop when the oscillator operates using the identified setting. The method further includes estimating a response of a loop filter in the phase-locked-loop and identifying one or more coefficients for a digital filter using the identified gain and the identified loop filter response. The digital filter is operable to filter an input signal. In addition, the method includes modulating the filtered input signal using the phase-locked-loop to produce an output signal.

US Patent:

6961400, Nov 1, 2005

Filed:

Aug 23, 2001

Appl. No.:

09/935940

Inventors:

William J. Huff - La Jolla CA, US
Lawrence J. Malone - Carlsbad CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L007/18

US Classification:

375376

Abstract:

A frequency shift keyed (FSK) receiver for demodulating an incoming transmitted signal comprising: 1) a phase-locked loop for receiving an oscillator reference signal having a frequency F1 and generating a reference carrier frequency signal having a desired frequency N1(F1), wherein N1 may be a non-integer value, the phase-locked loop comprising: a) a phase detector having a first input for receiving the oscillator reference signal and a second input; and b) a frequency divider circuit for dividing an actual frequency of the reference carrier frequency signal by an adjustable integer value N2 applied to a control input of the frequency divider circuit to generate a feedback signal applied to the second input of the phase detector. The FSK receiver further comprises: 2) a frequency discriminator that receives the incoming transmitted signal and the reference carrier frequency signal and generates a correction signal corresponding to a difference between a center frequency of the incoming transmitted signal and the actual frequency of the reference carrier frequency signal; and 3) a delta-sigma modulator controlled by the correction signal operable to generate a sequence of integers having an average value of N2 over a defined time period, wherein the sequence of integers are applied to the control input of the frequency divider circuit.

US Patent:

7075376, Jul 11, 2006

Filed:

Dec 20, 2004

Appl. No.:

11/017228

Inventors:

William J. Huff - La Jolla CA, US
Lawrence J. Malone - Carlsbad CA, US
Daniel R. Meacham - Del Mar CA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03L 7/00
H03C 3/06

US Classification:

331 23, 332128

Abstract:

A method includes identifying a setting for a capacitor bank associated with a voltage-controlled oscillator in a closed-loop phase-locked-loop. The setting represents a combination of one or more capacitors in the capacitor bank. The method also includes estimating a gain introduced by the closed-loop phase-locked-loop when the oscillator operates using the identified setting. The method further includes estimating a response of a loop filter in the phase-locked-loop and identifying one or more coefficients for a digital filter using the identified gain and the identified loop filter response. The digital filter is operable to filter an input signal. In addition, the method includes modulating the filtered input signal using the phase-locked-loop to produce an output signal.

US Patent:

7463097, Dec 9, 2008

Filed:

Dec 20, 2006

Appl. No.:

11/613216

Inventors:

Damian Costa - San Diego CA, US
William James Huff - San Diego CA, US

Assignee:

NXP B.V. - Eindhoven

International Classification:

H03B 5/04
H03B 5/12
H03L 1/02
H03L 7/099

US Classification:

331 14, 331 17, 331 36 C, 331176, 331177 V, 331179

Abstract:

Systems involving temperature compensation of voltage controlled oscillators are provided. In this regard, a representative system incorporates: a voltage controlled oscillator (VCO) having a tuning port and a phase-locked loop (PLL); and a temperature dependent voltage source. The VCO selectively exhibits one of a coarse tuning mode in which the temperature dependent voltage source is electrically connected to the VCO tuning port, and a locked mode in which the temperature dependent voltage source is not electrically connected to the VCO tuning port such that the PLL controls the frequency of the VCO.

US Patent:

20140070859, Mar 13, 2014

Filed:

Nov 15, 2013

Appl. No.:

14/081568

Inventors:

Michael Kappes - San Diego CA, US
William Huff - San Diego CA, US

Assignee:

IQ-Analog Corporation - San Diego CA

International Classification:

H03L 7/18

US Classification:

327158, 327156

Abstract:

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

US Patent:

20160380752, Dec 29, 2016

Filed:

Sep 30, 2015

Appl. No.:

14/871202

Inventors:

- Irvine CA, US
William HUFF - San Diego CA, US
Greg UNRUH - San Clemente CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00
H03L 7/18
H03L 7/085
H04L 7/033
H03L 7/099

Abstract:

The problem with duty-cycle correction circuits used by conventional frequency doubters is that they are typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.

US Patent:

20150109038, Apr 23, 2015

Filed:

Dec 8, 2014

Appl. No.:

14/562914

Inventors:

- San Diego CA, US
Michael Kappes - San Diego CA, US
William Huff - San Diego CA, US

International Classification:

H03L 7/091
H03L 7/18
H03M 1/06
H03L 7/093

US Classification:

327158, 327156

Abstract:

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

US Patent:

20150022384, Jan 22, 2015

Filed:

Oct 6, 2014

Appl. No.:

14/507563

Inventors:

- San Diego CA, US
Michael Kappes - San Diego CA, US
William Huff - San Diego CA, US

International Classification:

H03M 1/06
H03L 7/091
H03M 1/12

US Classification:

341118

Abstract:

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.