William T Ledbetter

US Patent:

58595414, Jan 12, 1999

Filed:

Sep 15, 1993

Appl. No.:

8/122193

Inventors:

Steven Craig McMahan - Garland TX
Kenneth Charles Scheuer - Austin TX
William Burl Ledbetter - Austin TX
Michael Gordon Gallup - Austin TX
James George Gay - Pflugerville TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1716
H03K 190175

US Classification:

326 30

Abstract:

A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

US Patent:

53177010, May 31, 1994

Filed:

Jan 19, 1993

Appl. No.:

8/005924

Inventors:

Russell Reininger - Austin TX
William B. Ledbetter - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 938

US Classification:

395375

Abstract:

A sequential prefetch method is provided for a pipelined data processor having a sequential instruction prefetch unit (IPU). An instruction queue in the IPU is coupled to a pipelined instruction unit and an instruction cache of the data processor. A prefetch controller in the IPU keeps the instruction stream prefetched so that the instruction queue may load any combination of one, two, or three word instructions into the pipelined instruction unit every clock cycle. The pipelined instruction unit receives instruction words from the instruction queue, and decodes the instruction for execution operations, and for the instruction length/pipeline movement. A queue filling method is provided for maintaining the requisite number of instruction words in the instruction queue to avoid pipeline stalls. The queue filling method is based upon the movement of the instruction pipeline attributable to the usage by an instruction sequencer of the instruction words received from the instruction queue.

US Patent:

51558246, Oct 13, 1992

Filed:

May 15, 1989

Appl. No.:

7/351899

Inventors:

Robin W. Edenfield - Austin TX
William B. Ledbetter - Austin TX
Russell A. Reininger - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1212
G06F 710

US Classification:

395425

Abstract:

A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (dirtiness). Multiple dirty bits provide a data cache controller with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory. The portions of the entry being replaced that are clean (unmodified) are not written to memory.

US Patent:

51856948, Feb 9, 1993

Filed:

Jun 26, 1989

Appl. No.:

7/371343

Inventors:

Robin W. Edenfield - Austin TX
Ralph McGarity - Austin TX
Russell Reininger - Austin TX
William B. Ledbetter - Austin TX
Van B. Shahan - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1328

US Classification:

395425

Abstract:

A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allows the programmer to fully utilize the maximum bus bandwidth of the system bus for memory to memory transfers of data (e. g. DMA, block moves, memory page initialization) and transfers of instructions/data to detached coprocessors.

US Patent:

51270897, Jun 30, 1992

Filed:

Jul 3, 1989

Appl. No.:

7/374906

Inventors:

James G. Gay - Pflugerville TX
William B. Ledbetter - Austin TX

Assignee:

Motorola, Inc. - Schaumberg IL

International Classification:

G06F 1342

US Classification:

395325

Abstract:

A data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed. The system has at least two processors coupled via the communication bus and a bus arbiter. In one form, a locked transfer end signal is provided by each processor to the bus arbiter so that if a high priority need is recognized by the bus arbiter during early execution of a plurality of locked operand transfer sequences the high priority need can be responded to by the bus arbiter before completion of all of the locked sequences. In another form, control signals are provided by the bus arbiter to each processor to accomplish the equivalent function.

US Patent:

50864076, Feb 4, 1992

Filed:

Jun 5, 1989

Appl. No.:

7/361539

Inventors:

Ralph C. McGarity - Austin TX
William B. Ledbetter - Austin TX
Steven C. McMahan - Austin TX
Michael G. Gallup - Austin TX
Russell Stanphill - Austin TX
James G. Gay - Pflugerville TX

International Classification:

G06F 1338

US Classification:

395800

Abstract:

A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.

US Patent:

52948455, Mar 15, 1994

Filed:

Aug 17, 1992

Appl. No.:

7/931187

Inventors:

Steven C. McMahan - Richardson TX
Kenneth C. Scheuer - Austin TX
William B. Ledbetter - Austin TX
Michael G. Gallup - Austin TX
James G. Gay - Pflugerville TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 19003

US Classification:

307443

Abstract:

A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

US Patent:

53768191, Dec 27, 1994

Filed:

Nov 29, 1993

Appl. No.:

8/158323

Inventors:

James G. Gay - Pflugerville TX
William B. Ledbetter - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2358
H01L 2966

US Classification:

257467

Abstract:

An integrated circuit implements an on chip thermal circuit (12) for measuring temperature of an operating integrated circuit die (10) by requiring only one dedicated integrated circuit pin (16). A second integrated circuit pin (18) is utilized but is also connected directly connected to other circuitry (14) on the integrated circuit and is used by the other circuitry at the same time that the integrated circuit die temperature is being measured. In one form, the second integrated circuit pin is a ground terminal. Error voltages coupled to the ground terminal may be removed from the temperature calculation by an external differential amplifier (24).