William J Liu

US Patent:

20020013932, Jan 31, 2002

Filed:

Jan 4, 2001

Appl. No.:

09/754811

Inventors:

William Liu - Plano TX, US
Mi-Chang Chang - Hsin-chu, TW

International Classification:

G06F017/50

US Classification:

716/004000, 716/005000

Abstract:

A continuous parametric model is provided for a physical circuit element that includes a base model which exhibits a discontinuity over an allowable range of model parameters or a discontinuity in the first derivative of the allowable range of model parameters. At least one compensation function can be provided to remove the discontinuities of the base model over the allowable range of parametric values and at least one compensation constant can be included to prevent a first derivative of the base model from exhibiting discontinuities over the allowable range of parameters, whereby the base model is rendered continuous. The resulting continuous parametric model provides enhanced simulation/analysis performance when compared to traditional smoothing functions.

US Patent:

6159816, Dec 12, 2000

Filed:

Jun 7, 1995

Appl. No.:

8/482034

Inventors:

Darrell G. Hill - Plano TX
Timothy S. Henderson - Richardson TX
William U. Liu - Plano TX
Hin-Fai Chau - Plano TX
Damian Costa - Dallas TX
Ali Khatibzadeh - Plano TX

Assignee:

TriQuint Semiconductor Texas, Inc. - Hillsboro OR

International Classification:

H01L 21331

US Classification:

438309

Abstract:

A bipolar transistor includes a passivating layer of material 40 in the base structure 42 that serves to cover the extrinsic base region of the transistor. The passivating layer 40 is formed of a material having a wider bandgap than the base layer 44, and is heavily doped with the same doping type (n or p) as the base layer. The invention is advantageous in that the base contacts 48 of the device are made directly to the passivating layer 40 and are not in direct contact with the base layer 44. This eliminates the need for alloyed contacts and the concomitant reliability problems associated with spiking contacts. In addition, the invention is completely compatible with self-aligned production techniques.

US Patent:

56169507, Apr 1, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/475157

Inventors:

William U. Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2970
H01L 29772

US Classification:

257469

Abstract:

Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.

US Patent:

56843100, Nov 4, 1997

Filed:

Aug 10, 1993

Appl. No.:

8/104743

Inventors:

William Uei-Chunt Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 310328

US Classification:

257197

Abstract:

Generally, and in one form of the invention, a multiple layer wide bandgap collector structure is provided which comprises a relatively thin, highly doped layer 12 and a relatively thick, low doped or non-intentionally doped layer 14. Other devices, systems and methods are also disclosed.

US Patent:

52780830, Jan 11, 1994

Filed:

Oct 16, 1992

Appl. No.:

7/962433

Inventors:

Darrell G. Hill - Plano TX
William U. Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2970

US Classification:

437 31

Abstract:

Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.

US Patent:

54554403, Oct 3, 1995

Filed:

May 17, 1994

Appl. No.:

8/245712

Inventors:

Timothy S. Henderson - Richardson TX
William U. Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218222
H01L 29737

US Classification:

257198

Abstract:

Generally, and in one form of the invention, a method is disclosed for reducing base-to-emitter leakage in a bipolar transistor having an active region 22 bounded by an isolation implant boundary 24, said method comprising arranging an emitter contact 26 and a base contact 36 such that at a crossing of the contacts over the implant boundary, a leakage current between the contacts along the boundary is limited by a necessity to transit the thickness of a layer of material, and whereby said transistor exhibits improved gain, noise performance, and reliability.

US Patent:

52984397, Mar 29, 1994

Filed:

Dec 31, 1992

Appl. No.:

7/999076

Inventors:

William U.-C. Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

A method of making a transistor comprising the steps of providing a structure having a collector layer 3, a base layer 5, and an emitter layer 7, one atop the other, forming a contact 9 on the emitter layer, removing a portion of the emitter layer to leave a relatively thick mesa region 13 with the contact thereon, a surrounding relatively thin ledge region 11 and an exposed portion of the base layer 5 and forming a contact on the exposed portion of the base layer 5. The emitter layer 7 is preferably GaInP, and preferably Ga. sub. x In. sub. 1-x P, wherein x is in the range of approximately 0. 50 to 0. 52, and the base 5 is preferably GaAs. The ledge portion 11 has a thickness of about 700 Angstroms.

US Patent:

55717322, Nov 5, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/474272

Inventors:

William U. Liu - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

In one form of the invention, a bipolar transistor is disclosed, the transistor comprising a GaAs substrate in the (111) orientation 100, and an InGaAs region 106 over the substrate 100, the InGaAs region 106 having a first surface and a second surface, wherein the mole fraction of In in the InGaAs region 106 varies from said first surface to said second surface.