William J Marble

US Patent:

6356148, Mar 12, 2002

Filed:

Jul 18, 2000

Appl. No.:

09/620277

Inventors:

William J. Marble - Provo UT

Assignee:

AMI Semiconductor, Inc. - Pocatello ID

International Classification:

H03F 102

US Classification:

330 9, 327124

Abstract:

A charge transfer amplifier includes a first stage charge transfer amplifier coupled to a positive capacitive feedback mechanism. The positive capacitive feedback mechanism is attached to the output terminal of a first stage charge transfer amplifier. This reduces the capacitance viewed at the output terminal of the first stage charge transfer capacitor thus increasing the overall gain of the charge transfer amplifier. The positive capacitive feedback mechanism includes a second stage amplifier having an output terminal capacitively coupled back to the output terminal of the first stage charge transfer amplifier. The coupling of the positive capacitive feedback mechanism to the charge transfer amplifier allows for enhanced amplifier gain while still retaining the beneficial characteristics of charge transfer amplifiers generally.

US Patent:

6566943, May 20, 2003

Filed:

Dec 26, 2001

Appl. No.:

10/034801

Inventors:

William J. Marble - Provo UT

Assignee:

AMI Semiconductor, Inc. - Pocatello ID

International Classification:

H03F 102

US Classification:

330 9, 327124

Abstract:

A charge transfer amplifier that performs amplification without a selective coupling to a precharge reference voltage. In lieu of the selective precharge coupling, the drain of the PMOS transistor is selectively coupled to Vss during the reset and precharge phases. In addition, the drain of the NMOS transistor is selectively coupled to Vss during the reset phase, and is selectively coupled to Vdd during the precharge phase. The drain of the PMOS transistor is capacitively coupled through a first intermediate capacitor to the output terminal of the charge transfer amplifier. The drain of the NMOS transistor is capacitively coupled through a second intermediate capacitor to the output terminal. During the amplify phase, the drains of the NMOS and PMOS transistor are permitted to float except for any charge flow through the respective transistor.

US Patent:

6606049, Aug 12, 2003

Filed:

Aug 2, 2002

Appl. No.:

10/211723

Inventors:

William J. Marble - Provo UT

Assignee:

AMI Semiconductor, Inc. - Pocatello ID

International Classification:

H03M 112

US Classification:

341155, 330 9, 327124

Abstract:

Transconveyance amplifiers, and more specifically charge transfer amplifiers, are included in analog-to-digital converters. Transconveyance amplifiers are used in averaging and interpolation circuits that facilitate converting an analog signal into a meaningful digital representation of the analog signal. Due to the characteristics of charge transfer amplifiers power dissipation in averaging and interpolation circuits is significantly reduced. Coupling capacitors associated with charge transfer amplifiers are utilized as analog sample and hold circuits for holding an analog signal while fine reference voltages settle. Thus, the need for separate sample and hold circuits is eliminated. A novel timing scheme allows an increased number of clock partitions for fine reference voltages to settle, thus providing for increased operational frequency. Residual charge imbalances at the input terminals of a latch are reduced in a manner that does not affect charge transfer amplifiers that are coupled to the latch during an amplify phase.

US Patent:

20010026604, Oct 4, 2001

Filed:

Mar 28, 2001

Appl. No.:

09/818777

Inventors:

William Marble - Santa Clara CA, US

Assignee:

General Electric Company

International Classification:

G21C009/00

US Classification:

376/306000

Abstract:

Method for controlling the introduction of zinc to a nuclear power reactor to control radiation build-up wherein zinc ions are introduced into the reactor water to counteract loss of zinc within the reactor system. In the process, the rate of introduction of zinc ions into the reactor water is balanced with the rate at which zinc ions are lost from the reactor.

US Patent:

20020191731, Dec 19, 2002

Filed:

May 28, 2002

Appl. No.:

10/155010

Inventors:

William Marble - Santa Clara CA, US

Assignee:

General Electric Company

International Classification:

G21C009/00

US Classification:

376/306000

Abstract:

Method for controlling the introduction of zinc to a nuclear power reactor to control radiation build-up wherein zinc ions are introduced into the reactor water to counteract loss of zinc within the reactor system. In the process, the rate of introduction of zinc ions into the reactor water is balanced with the rate at which zinc ions are lost from the reactor.

US Patent:

49504495, Aug 21, 1990

Filed:

Feb 26, 1988

Appl. No.:

7/160725

Inventors:

George E. Petersen - Fremont CA
Randall N. Robinson - San Jose CA
Carl P. Ruiz - Fremont CA
William J. Marble - Gilroy CA
Barry M. Gordon - Monte Sereno CA
Gerald M. Gordon - Soquel CA

Assignee:

General Electric Company - San Jose CA

International Classification:

G21C 900

US Classification:

376306

Abstract:

Deposition of radioactive cobalt on the interior surfaces of a water-cooled nuclear reactor and intergranular stress corrosion cracking are inhibited or substantially prevented by the continuous injection of zinc oxide to the reactor water. The zinc oxide may be prepared in the form of a paste, a slurry, or a preformed aqueous solution.

US Patent:

62491814, Jun 19, 2001

Filed:

Nov 30, 1999

Appl. No.:

9/451562

Inventors:

William J. Marble - Provo UT

International Classification:

H03F 102

US Classification:

330 9

Abstract:

A differential-mode charge transfer amplifier receives a differential input voltage and produces a proportional differential output voltage. The amplifier includes two CMOS charge transfer amplifiers. The two CMOS charge transfer amplifier share two charge transfer capacitors such that the CMOS charge transfer amplifiers are mirrored about the capacitors. The positive charge transfer capacitor terminal (i. e. , the terminal that is precharged to a high voltage) of one CMOS charge transfer amplifier is capacitively coupled to the negative charge transfer capacitor terminal (i. e. , the terminal that is precharged to a low voltage) of the other CMOS charge transfer amplifier. In addition, the negative charge transfer capacitor terminal of one CMOS charge transfer amplifier is capacitively coupled to the positive terminal of the other CMOS charge transfer amplifier. The amplifier has a significantly increased common-mode rejection, significantly reduced voltage amplification error, and an increased linearity range.