- San Jose CA, US Frederick A. Ware - Los Altos Hills CA, US William N. Ng - San Francisco CA, US
International Classification:
G11C 7/10 G11C 5/04
Abstract:
A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
Memory Module And System Supporting Parallel And Serial Access Modes
- Sunnyvale CA, US Frederick A. Ware - Los Altos Hills CA, US William N. Ng - San Francisco CA, US
International Classification:
G11C 7/10 G11C 5/04
Abstract:
A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
Memory Module And System Supporting Parallel And Serial Access Modes
- Sunnyvale CA, US Frederick A. Ware - Los Altos Hills CA, US William N. Ng - San Francisco CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
G06F 3/06 G06F 12/08
Abstract:
A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.
- Sunnyvale CA, US William N. Ng - San Francisco CA, US Frederick A. Ware - Los Altos Hills CA, US
Assignee:
Rambus Inc. - Sunnyvale CA
International Classification:
G11C 29/04 G11C 8/10 G01R 31/28
US Classification:
36523006
Abstract:
Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit.
Medicine Doctors
Dr. William Ng, San Francisco CA - MD (Doctor of Medicine)
Senior Unix System Administrator at Thomson Reuters
Location:
New York, New York
Industry:
Financial Services
Work:
Thomson Reuters since Oct 2006
Senior Unix System Administrator
Verizon Jun 2000 - Oct 2006
Consultant
AT&T Labs, Research and Development Feb 1998 - Jun 2000
System Administrator
Education:
Stevens Institute of Technology 1999 - 2000
M.S., Information System
State University of New York at Stony Brook 1994 - 1998
B.S., Computer Science
National Sales Manager at Yee Lee Trading Co. Sdn Bhd.
Location:
Penang, Malaysia
Industry:
Consumer Goods
Work:
Yee Lee Trading Co. Sdn Bhd. - Kuala Lumpur, Malaysia since May 2011
National Sales Manager
Permanis Sdn Bhd (bottler for Pepsico Malaysia) - Johore, Malaysia Nov 1998 - Oct 2009
Regional Manager
Education:
The University of Bolton 2006 - 2009
MBA, Supply Chain Management
TAR College 1982 - 1986
CIMA, Accountancy
Skills:
Distributed Team Management FMCG Trade Marketing Sales Management
Aug 2014 to 2000 Advisory Associate - Internal Audit Risk & ComplianceOPPORTUNITY TO ASSETS (OPTA) Los Angeles, CA Dec 2013 to Jun 2014 Program Consultant - Social EntrepreneurshipTHE WALT DISNEY COMPANY Glendale, CA Dec 2012 to Jun 2013 Accounting Intern - International AccountingBANK OF AMERICA MERRILL LYNCH Beverly Hills, CA Jul 2012 to Dec 2012 Financial Advisor Intern - Private Wealth ManagementTECHCRUNCH San Francisco, CA Oct 2011 to Dec 2012 CrunchBase Intern - Technology Startup News & AnalysisAQUA DESIGN INNOVATIONS San Francisco, CA Jul 2009 to Jan 2012 Co-founder - Aquatic Design & Servicing
Education:
UNIVERSITY OF CALIFORNIA Los Angeles, CA Jun 2014 Bachelor of Arts in Business Economics
Senior Principal Engineer, Product Engineering and Test at Rambus
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Rambus since Jan 2011
Senior Principal Engineer, Product Engineering and Test
Rambus Aug 2009 - Jan 2011
Senior Manager, System Technology
Rambus Aug 2008 - Aug 2009
Principal Engineer, Silicon Characterization
Rambus Apr 2007 - Aug 2008
Manager, Silicon Characterization
Rambus Apr 2004 - Aug 2007
Principal Engineer, System and Applications Engineering
Education:
University of California, Berkeley 1993 - 1997
BS, Electrical Engineering and Computer Science
St. Catharine of Alexandria School Brooklyn NY 1986-1992, Brooklyn Public School 131 Brooklyn NY 1993-1994, Mott Hall Intermediate School 223 New York NY 1995-1996
Health Authority - Intern (2013) WSAHS - Anaesthetics Registrar (2007-2011) Royal Melbourne Hospital - Cardiothoracic Anaesthetic Fellow (2012-2012) Prince of Wales Hospital, Chinese University of Hong Kong - Visiting Scholar in Anaesthesia (2012-2012)
Education:
University of New South Wales - MBBS, Macquarie University - BA
About:
Christian, child of the 80s, books, sounds, bach, running, cycling, hopeless linguist, theology over philosophy, modern history, political amateur, in need of fashion, films, ether, old sydneian, frie...
Tagline:
Seeking beauty, truth and permanence by banking on God's grace and glory
William Ng
Education:
Hong Kong Shue Yan College - BBA, Shue Yan University, Saint Louis School, Yu Chun Keung
William Ng
Work:
Suria Meriang Sdn. Bhd. - Data Entry Worker (2010-2010)
Education:
Kolej Tunku Abdul Rahman - STPM, Kolej Tunku Abdul Rahman - Cambridge A-Level
William Ng
Work:
Advanced Micro Devices (2008) Certicom Corp
William Ng
Work:
Marvel Entertainment - Help Desk Analyst (2010)
Education:
Hunter College - Computer Science
William Ng
Work:
Wei Teck Distribution - Sales Exec. (1997)
Education:
Manjusri Secondary
William Ng
Work:
NBCUniversal - Director, Technology - G4TV | Mobile (2009)
Tagline:
Just because you can, does not always mean you should...
Bragging Rights:
Was part of the Xboxâ„¢ Live Beta Test in 2002
William Ng
Work:
CITY University of Hong Kong - Business Mentor (2010) HKU SPACE - Adjunct Lecturer (2007)