William S Webster

US Patent:

6470228, Oct 22, 2002

Filed:

Jun 23, 1999

Appl. No.:

09/339334

Inventors:

Greg A. Turner - Arlington TX
Douglas K. Wolfe - Denton TX
Patrick S. Porowski - Duncanville TX
William Bruce Webster - Carrollton TX

Assignee:

Vought Aircraft Industries, Inc. - Dallas TX

International Classification:

G05B 19416

US Classification:

700 97, 700 98, 700107

Abstract:

A material management system and method ( ) includes a data storage device ( ) containing order information ( ) for a product, product information ( ) for a product, work center information ( ) for fabricating the product, and inventory information ( ) for fabricating the product. The system ( ) also includes a processor ( ) coupled to the data storage device ( ). The system ( ) further includes a nesting application ( ) operable for execution by the processor ( ). The nesting application ( ) is operable to determine a fabrication nest for the product using the order information ( ), the product information ( ), the work center information ( ), or the inventory information ( ).

US Patent:

41347994, Jan 16, 1979

Filed:

Jul 18, 1977

Appl. No.:

5/816562

Inventors:

Wallace B. Allen - Dallas TX
John W. Harrell - Duncanville TX
William W. Webster - Arlington TX

Assignee:

Mobil Oil Corporation - New York NY

International Classification:

G01N 2746

US Classification:

204 1T

Abstract:

A method for selecting a demulsifier for breaking a water-in-oil emulsion employs at least two electrodes to be immersed in a plurality of emulsion samples, each having a different demulsifier added. The current flow between the electrodes is recorded for each sample. The demulsifier producing the most rapid rate of change of current flow is identified as the most effective demulsifier in breaking the water-in-oil emulsion.

US Patent:

50417460, Aug 20, 1991

Filed:

Dec 20, 1989

Appl. No.:

7/453635

Inventors:

William S. Webster - Dallas TX
Daniel D. Edmondson - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03R 1704

US Classification:

307530

Abstract:

A sense amplifier (38) uses a current source (40) to pull-up a product line (14) during as low-to-high transition. After a desired voltage is reached on the product line (14), the current source is turned off by a delay feedback circuit (44). A hold-up circuit (42) holds the product line at the desired voltage until a high-to-low transition occurs.

US Patent:

54883172, Jan 30, 1996

Filed:

Oct 22, 1993

Appl. No.:

8/141339

Inventors:

William S. Webster - Dallas TX
David D. Wilmoth - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19088
H03K 19094

US Classification:

326 45

Abstract:

An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connected to a signal (I/O) when no wired outputs (y) are desired. If two or more outputs (y) are to be connected to enable a wired logic function, p-channel transistor (16) is disabled. Then, a weak pull-up transistor (18) may be provided. Alternatively, a senseamp may be provided to the connected outputs (y).

US Patent:

53999231, Mar 21, 1995

Filed:

Jul 26, 1993

Appl. No.:

8/096324

Inventors:

William S. Webster - Dallas TX
David D. Wilmoth - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19177
H01H 3776

US Classification:

326 38

Abstract:

A field programmable gate array (10) having a plurality of logic modules (31-35) has a pair of driver circuits (51-52) connected between each logic module (31) and logic module interconnection tracks or lines (12-16, 20-23) (51-52). Each of the drivers (51-52) has an input connected to receive a common output signal from the associated logic module (31). The output from each of the driver circuits (51-52) is selectively connectable to one of the interconnection tracks by a different respective antifuse (27). The output of each driver circuit (51-52) has a current magnitude less than a level that would damage the antifuse (27) but greater than a predetermined level, so that the track capacitances can be charged as rapidly as possible to increase the propagation time of a signal in the array. In one embodiment (10), the respective logic module interconnection lines or tracks 12 to which the pair of antifuses are connected are different logic module interconnection lines (12, 13). In another embodiment (150), the respective logic module interconnection lines to which the pair of antifuses (185, 186) are connected are the same logic module interconnection line or track (186).