Winnie L Yeung

US Patent:

8098255, Jan 17, 2012

Filed:

May 22, 2009

Appl. No.:

12/470712

Inventors:

Farhad Fouladi - Los Altos Hills CA, US
Winnie W. Yeung - San Jose CA, US
Howard Cheng - Sammamish WA, US

Assignee:

Nintendo Co., Ltd. - Kyoto

International Classification:

G09G 5/36
G06F 13/18
G06F 13/00

US Classification:

345558, 345535, 345536

Abstract:

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller performs a wide range of memory control related functions including arbitrating between various competing resources seeking access to main memory, handling memory latency and bandwidth requirements of the resources requesting memory access, buffering writes to reduce bus turn around, refreshing main memory, and protecting main memory using programmable registers. The memory controller minimizes memory read/write switching using a “global” write queue which queues write requests from various diverse competing resources. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained. Memory coherency issues are addressed both within a single resource that has both read and write capabilities and among different resources by efficiently flushing write buffers associated with a resource.

US Patent:

7538772, May 26, 2009

Filed:

Nov 28, 2000

Appl. No.:

09/726220

Inventors:

Farhad Fouladi - Los Altos Hills CA, US
Winnie W. Yeung - San Jose CA, US
Howard Cheng - Sammamish WA, US

Assignee:

Nintendo Co., Ltd. - Kyoto

International Classification:

G06F 13/18
G09G 5/39
G06F 13/00

US Classification:

345535, 345531, 711100

Abstract:

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller performs a wide range of memory control related functions including arbitrating between various competing resources seeking access to main memory, handling memory latency and bandwidth requirements of the resources requesting memory access, buffering writes to reduce bus turn around, refreshing main memory, and protecting main memory using programmable registers. The memory controller minimizes memory read/write switching using a “global” write queue which queues write requests from various diverse competing resources. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained. Memory coherency issues are addressed both within a single resource that has both read and write capabilities and among different resources by efficiently flushing write buffers associated with a resource.

US Patent:

20210295593, Sep 23, 2021

Filed:

Jun 4, 2021

Appl. No.:

17/338846

Inventors:

- Cupertino CA, US
Karl D. Mann - Geneva FL, US
Tyson J. Bergland - Sunnyvale CA, US
Winnie W. Yeung - San Jose CA, US

International Classification:

G06T 15/80
G06T 15/00
G06T 15/04
G09G 5/36

Abstract:

Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

US Patent:

20210134052, May 6, 2021

Filed:

Nov 4, 2019

Appl. No.:

16/673883

Inventors:

- Cupertino CA, US
Karl D. Mann - Geneva FL, US
Tyson J. Bergland - Sunnyvale CA, US
Winnie W. Yeung - San Jose CA, US

International Classification:

G06T 15/80
G06T 15/00
G06T 15/04
G09G 5/36

Abstract:

Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.

US Patent:

20190266102, Aug 29, 2019

Filed:

May 13, 2019

Appl. No.:

16/410828

Inventors:

- Cupertino CA, US
Kenneth C. Dyke - Los Altos CA, US
Karthik Ramani - San Jose CA, US
Winnie W. Yeung - San Jose CA, US
Anthony P. DeLaurier - Los Altos CA, US
Luc R. Semeria - Palo Alto CA, US
David A. Gotwalt - Winter Springs FL, US
Srinivasa Rangan Sridharan - San Jose CA, US
Muditha Kanchana - San Jose CA, US

International Classification:

G06F 12/123
G06F 12/0815
G06F 12/0804
G06F 12/0808

Abstract:

Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.

US Patent:

20180349291, Dec 6, 2018

Filed:

May 31, 2017

Appl. No.:

15/610008

Inventors:

- Cupertino CA, US
Kenneth C. Dyke - Los Altos CA, US
Karthik Ramani - San Jose CA, US
Winnie W. Yeung - San Jose CA, US
Anthony P. DeLaurier - Los Altos CA, US
Luc R. Semeria - Palo Alto CA, US
David A. Gotwalt - Winter Springs FL, US
Srinivasa Rangan Sridharan - San Jose CA, US
Muditha Kanchana - San Jose CA, US

International Classification:

G06F 12/123
G06F 12/0808
G06F 12/0815
G06F 12/0804

Abstract:

Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.