Xiao Qi Zhang

US Patent:

7161759, Jan 9, 2007

Filed:

Apr 19, 2002

Appl. No.:

10/127015

Inventors:

Xiao (John) Zhang - Cupertino CA, US
Lin Guo - Milpitas CA, US

Assignee:

Maxtor Corporation - Scotts Valley CA

International Classification:

G11B 21/02
G11B 5/596

US Classification:

360 75, 360 7704

Abstract:

The present invention provides self-servo writing by which self-propagated servo pattern track shape errors are reduced or eliminated. The method includes providing first servo bursts on a first track, measuring edge errors of the first servo bursts, and self-servo writing second servo bursts to a second track using different combinations of the edge errors to adjust the position error signals for the second servo bursts.

US Patent:

7208818, Apr 24, 2007

Filed:

Jul 20, 2004

Appl. No.:

10/896375

Inventors:

Leeshawn Luo - Santa Clara CA, US
Anup Bhalla - Santa Clara CA, US
Sik K. Lui - Sunnyvale CA, US
Yueh-Se Ho - Sunnyvale CA, US
Mike F. Chang - Cupertino CA, US
Xiao Tian Zhang - San Jose CA, US

Assignee:

Alpha and Omega Semiconductor Ltd. - Hamilton

International Classification:

H01L 23/495

US Classification:

257666, 257676, 257E23037

Abstract:

A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

US Patent:

7394151, Jul 1, 2008

Filed:

Feb 15, 2005

Appl. No.:

11/058913

Inventors:

Leeshawn Luo - Santa Clara CA, US
Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US
Xiao Tian Zhang - San Jose CA, US

Assignee:

Alpha & Omega Semiconductor Limited - Sunnyvale CA

International Classification:

H01L 23/48

US Classification:

257690, 257693, 257E21511

Abstract:

A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

US Patent:

7633140, Dec 15, 2009

Filed:

Dec 9, 2003

Appl. No.:

10/732181

Inventors:

Leeshawn Luo - Santa Clara CA, US
Anup Bhalla - Santa Clara CA, US
Sik K. Lui - Sunnyvale CA, US
Yueh-Se Ho - Sunnyvale CA, US
Mike F. Chang - Cupertino CA, US
Xiao Tiang Zhang - San Jose CA, US

Assignee:

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

International Classification:

H01L 23/495

US Classification:

257666, 257787

Abstract:

A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.

US Patent:

7800369, Sep 21, 2010

Filed:

May 30, 2008

Appl. No.:

12/130214

Inventors:

Xiao Zhang - Cupertino CA, US
John S. Tobias - Campbell CA, US

Assignee:

Varian, Inc. - Santa Clara CA

International Classification:

G01V 3/00

US Classification:

324318

Abstract:

Remote adjustment of a selected one of a plurality of adjustable NMR probe circuit components is achieved with a plurality of selectable linear actuators, the selected one of which urges a platen against a respective driven gear, azimuthally locked to its shaft, to displace it axially along that shaft. When the driven gear engages a driving gear a single driving motor is energized and controlled to effect the desired adjustment.

US Patent:

7897438, Mar 1, 2011

Filed:

May 22, 2008

Appl. No.:

12/154537

Inventors:

Leeshawn Luo - Santa Clara CA, US
Kai Liu - Sunnyvale CA, US
Ming Sun - Sunnyvale CA, US
Xiao Tian Zhang - San Jose CA, US

Assignee:

Alpha and Omega Semiconductor Incorporated - Sunnyvale CA

International Classification:

H01L 21/00

US Classification:

438125, 438127, 438612, 257690, 257693, 257E21511

Abstract:

A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

US Patent:

8429665, Apr 23, 2013

Filed:

Mar 19, 2010

Appl. No.:

12/727705

Inventors:

Puneet Zaroo - Santa Clara CA, US
Richard West - Easton MA, US
Carl A. Waldspurger - Palo Alto CA, US
Xiao Zhang - Rochester NY, US

Assignee:

VMware, Inc. - Palo Alto CA

International Classification:

G06F 9/50

US Classification:

718104, 718102

Abstract:

A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.

US Patent:

8564049, Oct 22, 2013

Filed:

Mar 31, 2008

Appl. No.:

11/894240

Inventors:

Ming Sun - Sunnyvale CA, US
Kai Liu - Sunnyvale CA, US
Xiao Tian Zhang - San Jose CA, US
Yueh Se Ho - Sunnyvale CA, US
Leeshawn Luo - Santa Clara CA, US

Assignee:

Alpha & Omega Semiconductor Incorporated - Sunnyvale CA

International Classification:

H01L 29/66

US Classification:

257329, 257600

Abstract:

This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.