Xiao S Zhang

US Patent:

20050076220, Apr 7, 2005

Filed:

Jan 5, 2004

Appl. No.:

10/707694

Inventors:

Xiao Quan Zhang - Cambridge MA, US
Gordon Mo - Prospect Heights IL, US

International Classification:

H04L009/00

US Classification:

713176000

Abstract:

A method and system for issuing fingerprint keys and anti-spam points to meet the needs of email marketers to get their legitimate emails delivered without spamming recipients. Minimum modification to the recipient's email server is introduced to enable it to communicate with servers for registration/authentication purposes. For every email sent from a sender to a recipient using the system built upon the present invention, the sender's allotment of anti-spam points would be deducted by a fixed or varied number, depending on the specific implementation of the particular embodiment of the present invention. The method allows advertisers to buy anti-spam points from the service provider and provides a method to redistribute the payment to recipients of the advertisements.

US Patent:

20100095300, Apr 15, 2010

Filed:

Oct 14, 2008

Appl. No.:

12/251108

Inventors:

Richard West - Easton MA, US
Puneet Zaroo - Santa Clara CA, US
Carl A. Waldspurger - Palo Alto CA, US
Xiao Zhang - Rochester NY, US
Haoqiang Zheng - Sunnyvale CA, US

Assignee:

VMWARE, INC. - Palo Alto CA

International Classification:

G06F 9/50
G06F 9/46

US Classification:

718104, 718102, 709226

Abstract:

Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread. In another embodiment, cache miss-rate curves are constructed for a thread to help analyze performance tradeoffs when changing cache allocations of the threads in the system.

US Patent:

20110055479, Mar 3, 2011

Filed:

Aug 28, 2009

Appl. No.:

12/550193

Inventors:

Richard West - Easton MA, US
Puneet Zaroo - Santa Clara CA, US
Carl A. Waldspurger - Palo Alto CA, US
Xiao Zhang - Rochester NY, US

Assignee:

VMware, Inc. - Palo Alto CA

International Classification:

G06F 9/46
G06F 12/08

US Classification:

711118, 718103, 711E12017

Abstract:

A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.

US Patent:

20130232500, Sep 5, 2013

Filed:

Mar 29, 2013

Appl. No.:

13/853734

Inventors:

Richard WEST - Easton MA, US
Carl A. WALDSPURGER - Palo Alto CA, US
Xiao ZHANG - Rochester NY, US

Assignee:

VMware, Inc. - Palo Alto CA

International Classification:

G06F 9/48
G06F 9/50

US Classification:

718104, 718102

Abstract:

A method is described for scheduling in an intelligent manner a plurality of threads on a processor having a plurality of cores and a shared last level cache (LLC). In the method, a first and second scenario having a corresponding first and second combination of threads are identified. The cache occupancies of each of the threads for each of the scenarios are predicted. The predicted cache occupancies being a representation of an amount of the LLC that each of the threads would occupy when running with the other threads on the processor according to the particular scenario. One of the scenarios is identified that results in the least objectionable impacts on all threads, the least objectionable impacts taking into account the impact resulting from the predicted cache occupancies. Finally, a scheduling decision is made according to the one of the scenarios that results in the least objectionable impacts.

US Patent:

20160133839, May 12, 2016

Filed:

Jun 13, 2014

Appl. No.:

14/896870

Inventors:

- New Brunswick NJ, US
Xiao Zhang - Piscataway NJ, US
George Z. Wei - North Brunswick NJ, US
Wei Liu - New Brunswick NJ, US

International Classification:

H01L 51/00
C09K 11/06
C07F 1/08

Abstract:

Inorganic-organic hybrid IB-VII semiconductor compounds, in which a Group IB transition metal halide salt is coordinated with an organic heteroaromatic ligand, wherein at least one ring atom of said heteroaromatic ligand is a heteroatom independently selected from N, O and S and the Group IB metal of the halide salt is coordinated to a ring heteroatom. Also disclosed are semiconductor and light emitting devices comprising these materials, including light emitting diodes, and methods of preparing these materials and devices.