Xiao Y Zheng

US Patent:

8566628, Oct 22, 2013

Filed:

May 6, 2009

Appl. No.:

12/436439

Inventors:

Alexander Branover - Chestnut Hill MA, US
Maurice B. Steinman - Marlborough MA, US
Ming L. So - Danville CA, US
Xiao Gang Zheng - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/32

US Classification:

713323, 713310, 713324, 713330

Abstract:

A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.

US Patent:

20130227196, Aug 29, 2013

Filed:

Feb 27, 2012

Appl. No.:

13/405957

Inventors:

Xiao Gang Zheng - Sunnyvale CA, US
Ming L. So - Danville CA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 12/00
G06F 3/00
G06F 13/36

US Classification:

711103, 710306, 710 10, 711E12008

Abstract:

A circuit for use in a computing system including and a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof.

US Patent:

20130262726, Oct 3, 2013

Filed:

Mar 28, 2012

Appl. No.:

13/432178

Inventors:

Xiao Gang Zheng - Sunnyvale CA, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 13/26

US Classification:

710264

Abstract:

Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method.

US Patent:

20220363694, Nov 17, 2022

Filed:

Aug 13, 2019

Appl. No.:

17/266466

Inventors:

- Thousand Oaks CA, US
- Berkeley CA, US
Russell GRACEFFA - Hampton CA, US
Jeffrey IWIG - Albany CA, US
Joon Won JEONG - Belmont CA, US
Ryan D. WHITE - Somerville MA, US
Yongwei WU - Belmont CA, US
Shuyan YI - Malden MA, US
Xiao Mei ZHENG - Dover MA, US
Jesse M. MCFARLAND - Berkeley CA, US
Abhisek BANERJEE - Bangalore, Karnataka, IN

Assignee:

Amgen Inc. - Thousand Oaks CA
Carmot Therapeutics, Inc. - Berkeley CA

International Classification:

C07D 519/00
C07D 487/18

Abstract:

The present invention provides a compound of formula (I) or a pharmaceutically acceptable salt thereof, pharmaceutical compositions comprising a compound of the invention, a method for manufacturing compounds of the invention and therapeutic uses thereof.

US Patent:

20190265774, Aug 29, 2019

Filed:

Feb 28, 2018

Appl. No.:

15/907660

Inventors:

- Santa Clara CA, US
- Markham, CA
Ming L. So - Danville CA, US
Philip Ng - Toronto, CA
Xiao Gang Zheng - Sunnyvale CA, US
Felix Ho - Toronto, CA
Joseph Scanlon - Sunnyvale CA, US
Christopher T. Weaver - Boxborough MA, US
Xiaojie He - Austin TX, US
Carl Kittredge Wakeland - Scotts Valley CA, US

International Classification:

G06F 1/32

Abstract:

Systems, apparatuses, and methods for aligning active and idle phases of components in a computing system are disclosed. A computing system includes components that can be forced into an active or idle phase and components that cannot be forced into an active or idle phase. The system implements schemes for aligning the active and idle phases of the components within the system. For example, a timer starts counting when a processor and memory subsystem go from a low power state to an operational state. If the amount of time spent by the processor and memory subsystems in the operational state without transitioning to the low power state exceeds a threshold, the system forces active-to-idle and idle-to-active phase transitions of components in the system in order to cause a realignment of active and idle phases of the various components within the system.

US Patent:

20140310552, Oct 16, 2014

Filed:

Apr 15, 2013

Appl. No.:

13/862854

Inventors:

- Sunnyvale CA, US
Xiao Gang Zheng - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/32
G06F 3/06

US Classification:

713324, 711162, 711105

Abstract:

Current computer systems support sleep states such as sleep state S and sleep state S A system in sleep state S utilizes more power than one in sleep state S however, a system in sleep state S can resume function substantially faster than a system in sleep state S An idle system is often put into sleep state S rather than sleep state S because of the shorter resume time even though sleep state S utilizes more power. Embodiments include a reduced-power sleep state S that uses less power than sleep state S yet resumes function faster than sleep state S Embodiments reduce the power consumed by compressing and consolidating system context to fewer memory modules, and powering down unused memory modules. Embodiments thus avoid storing system content to non-volatile memory. Embodiments include waking the system by restoring system context in the reverse order to respective memory modules.