Xiaosong Liu Xin Wang

US Patent:

20230061998, Mar 2, 2023

Filed:

Aug 27, 2021

Appl. No.:

17/459644

Inventors:

- Santa Clara CA, US
Andriy Myronenko - San Francisco CA, US
Xiaosong Wang - Rockville MD, US
Ziyue Xu - Reston VA, US
Holger Roth - Rockville MD, US
Daguang Xu - Potomac MD, US

International Classification:

G06K 9/62
G06N 3/08
G06N 3/04
G06F 7/24

Abstract:

Apparatuses, systems, and techniques are presented to select neural networks. In at least one embodiment, one or more first neural networks can be used to select one or more second neural networks, as may be based at least in part upon an inference to be generated by the one or more second neural networks.

US Patent:

20230033075, Feb 2, 2023

Filed:

Jul 13, 2021

Appl. No.:

17/374384

Inventors:

- Santa Clara CA, US
Andriy Myronenko - San Francisco CA, US
Dong Yang - Pocatello ID, US
Holger Reinhard Roth - Rockville MD, US
Can Zhao - North Potomac MD, US
Xiaosong Wang - Rockville MD, US
Daguang Xu - Potomac MD, US

International Classification:

G06T 7/11
G06N 3/08
G06N 3/04
G06T 7/00
G16H 30/40
G06K 9/62

Abstract:

Apparatuses, systems, and techniques are presented to predict annotations for objects in images. In at least one embodiment, boundaries of an object within an image can be identified based, at least in part, on a user-generated outline of only a portion of this object or information about a size of this object provided by a user.

US Patent:

20210264257, Aug 26, 2021

Filed:

Feb 28, 2019

Appl. No.:

16/975685

Inventors:

- Fremont CA, US
Xiaosong WANG - Fremont CA, US
Tong WU - Fremont CA, US
Steven SERTILLANGE - San Leandro CA, US

International Classification:

G06N 3/08
G06N 3/063
G06F 7/544

Abstract:

An AI (Artificial Intelligence) processor for Neural Network (NN) Processing shared by multiple users is disclosed. The AI processor comprises a Multiplier Unit (MXU), a Scalar Computing Unit (SCU), a unified buffer coupled to the MXU and SCU to store data and a control circuitry coupled to the CCU and the unified buffer. The MXU comprises a plurality of Processing Elements (PEs) responsible for computing matrix multiplications. The SCU coupled to output of the MXU is responsible for computing the activation function. The control circuitry is configured to perform the space division and time division NN processing for a plurality of users. At one time instance, at least one of the MXU and SCU is shared by two or more users; and at least one user is using a part of the MXU while the other user is using a part of the SCU.

US Patent:

20210141697, May 13, 2021

Filed:

Feb 25, 2019

Appl. No.:

16/976063

Inventors:

- Fremont CA, US
Yujie HU - Fremont CA, US
Tong WU - Fremont CA, US
Clifford GOLD - Fremont CA, US
Yick Kei WONG - Union City CA, US
Xiaosong WANG - Fremont CA, US
Steven SERTILLANGE - San Leandro CA, US
Zongwei ZHU - Sunnyvale CA, US

International Classification:

G06F 11/14
G06N 3/04
G06F 11/10
G06F 13/42

Abstract:

Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes multiple types of HEs (hardware elements) comprising one or more HEs configured to perform operations associated with multi-layer NN (neural network) processing, at least one spare HE, a data buffer to store correctly computed data in a previous layer of multi-layer NN processing computed, and fault tolerance (FT) control logic. The FT control logic is configured to: determine a fault in a current layer NN processing associated with the HE; cause the correctly computed data in the previous layer of multi-layer NN processing to be copied or moved to said at least one spare HE; and cause said at least one spare HE to perform the current layer NN processing using said at least one spare HE and the correctly computed data in the previous layer of multi-layer NN processing.

US Patent:

20190279083, Sep 12, 2019

Filed:

Apr 19, 2018

Appl. No.:

15/956988

Inventors:

- Fremont CA, US
Tong Wu - Fremont CA, US
Yujie Hu - Fremont CA, US
Chung Kuang Chin - Saratoga CA, US
Xiaosong Wang - Fremont CA, US
Yick Kei Wong - Union City CA, US

International Classification:

G06N 3/08
G06F 7/544
G06N 3/063

Abstract:

A computing device for fast weighted sum calculation in neural networks is disclosed. The computing device comprises an array of processing elements configured to accept an input array. Each processing element comprises a plurality of multipliers and a multiple levels of accumulators. A set of weights associated with the inputs and a target output are provided to a target processing element to compute the weighted sum for the target output. The device according to the present invention reduces the computation time from M clock cycles to logM, where M is the size of the input array.

US Patent:

20190227887, Jul 25, 2019

Filed:

Jun 5, 2018

Appl. No.:

16/000718

Inventors:

- Grand Cayman, KY
Tong Wu - Fremont CA, US
Xiaosong Wang - Fremont CA, US
Zongwei Zhu - Sunnyvale CA, US
Chung Kuang Chin - Saratoga CA, US
Clifford Gold - Fremont CA, US
Steven Sertillange - San Leandro CA, US
Yick Kei Wong - Union City CA, US

Assignee:

DinoplusAI Holdings Limited - Grand Cayman

International Classification:

G06F 11/20
G06F 1/32
G06F 1/26
G06N 3/04

Abstract:

Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes an instruction buffer, processing circuitry, a data buffer, command circuitry, and communication circuitry. During operation, the instruction buffer stores a first hardware instruction and a second hardware instruction. The processing circuitry executes the first hardware instruction, which computes an intermediate stage of an AI model. The data buffer stores data generated from executing the first hardware instruction. The command circuitry determines that the second hardware instruction is a hardware-initiated store instruction for transferring the data from the data buffer. Based on the hardware-initiated store instruction, the communication circuitry transfers the data from the data buffer to a memory device of a computing system, which includes the mission-critical processor, via a communication interface.