Xiaozhu Te Kang

US Patent:

20130159680, Jun 20, 2013

Filed:

Dec 19, 2011

Appl. No.:

13/330359

Inventors:

Wei-yu Chen - San Jose CA, US
Kaiyu Chen - Santa Clara CA, US
Xiaozhu Kang - Fremont CA, US

International Classification:

G06F 9/302
G06F 9/315

US Classification:

712222, 712E09017, 712E09034

Abstract:

Methods, systems, and computer program products for the performance of arithmetic operations on large numbers. The addition of large numbers may be parallelized by adding corresponding sections of the numbers in parallel. The multiplication of large numbers may be accomplished by applying a multiplier to a multiplicand after the latter is divided into sections, where the multiplication of the sections is performed in parallel. Products for each section are saved in high and low order vectors, which may then be aligned and added. The comparison of two large numbers may be performed by comparing the numbers, section by section, in parallel. In an embodiment, these processes may be performed in a graphics processing unit (GPU) having multiple cores. In an embodiment, such a GPU may be integrated into a larger die that also incorporates one or more conventional central processing unit (CPU) cores.

US Patent:

20130297919, Nov 7, 2013

Filed:

Nov 30, 2011

Appl. No.:

13/997239

Inventors:

Xiaozhu Kang - Fremont CA, US
Biju George - San Jose CA, US
Ken Lueh - San Jose CA, US

International Classification:

G06F 9/38

US Classification:

712241

Abstract:

Various embodiments are directed to a heterogeneous processor architecture comprised of a CPU and a GPU on the same processor die. The heterogeneous processor architecture may optimize source code in a GPU compiler using vector strip mining to reduce instructions of arbitrary vector lengths into GPU supported vector lengths and loop peeling. It may be first determined that the source code is eligible for optimization if more than one machine code instruction of compiled source code under-utilizes GPU instruction bandwidth limitations. The initial vector strip mining results may be discarded and the first iteration of the inner loop body may be peeled out of the loop. The type of operands in the source code may be lowered and the peeled out inner loop body of source code may be vector strip mined again to obtain optimized source code.

US Patent:

20160110554, Apr 21, 2016

Filed:

Dec 4, 2014

Appl. No.:

14/560245

Inventors:

Xiaozhu Kang - Fremont CA, US
Karanvir S. Grewal - Hillsboro OR, US

International Classification:

G06F 21/60
G06F 21/83
G06F 3/041

Abstract:

Technologies for secure input and display of a virtual touch user interface include a computing device having a security monitor that may protect memory regions from being accessed by untrusted code. The security monitor may use hardware virtualization features such as extended page tables or directed I/O to protect the memory regions. A protected touch filter driver intercepts requests for touch input and allocates a transfer buffer. The transfer buffer is protected by the security monitor. A touch screen controller may write touch input data into the protected transfer buffer. The touch input data may be shared by the touch filter driver with authorized applications through a protected communication channel. A graphical virtual user interface may be generated by trusted code and rendered into a hardware overlay surface. The user interface may include a virtual keyboard. The security monitor may protect the overlay surface. Other embodiments are described and claimed.

US Patent:

20140337983, Nov 13, 2014

Filed:

May 10, 2013

Appl. No.:

13/891255

Inventors:

Xiaozhu Kang - Fremont CA, US
Alpa T. Narendra Trivedi - Hillsboro OR, US
Siddhartha Chhabra - Hillsboro OR, US
Prashant Dewan - Hillsboro OR, US
Uday R. Savagaonkar - Portland OR, US
David M. Durham - Beaverton OR, US

International Classification:

G06F 21/60

US Classification:

726 26

Abstract:

The entry/exit architecture may be a critical component of a protection framework using a secure enclaves-like trust framework for coprocessors. The entry/exit architecture describes steps that may be used to switch securely into a trusted execution environment (entry architecture) and out of the trusted execution environment (exit architecture), at the same time preventing any secure information from leaking to an untrusted environment.