Xin Zhang

Address:

5941 Glendower Ln, Plano, TX 75093

VIN:

5FNYF4H45BB094509

Make:

HONDA

Model:

PILOT

Year:

2011

US Patent:

6797593, Sep 28, 2004

Filed:

Sep 13, 2002

Appl. No.:

10/243610

Inventors:

Srinivasan Chakravarthi - Richardson TX
Amitabh Jain - Richardson TX
Xin Zhang - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21425

US Classification:

438514, 438530, 438527

Abstract:

Methods are described for fabricating MOS type transistors, in which multiple drain extension implants are performed using different dopant species of the same type. The implanted drain extension dopants are activated using separate anneal processes to provide active dopants of both species throughout the drain extension regions adjacent the transistor channel.

US Patent:

7033879, Apr 25, 2006

Filed:

Apr 29, 2004

Appl. No.:

10/835121

Inventors:

Brian E. Hornung - Richardson TX, US
Xin Zhang - Plano TX, US
Lance S. Robertson - Rockwall TX, US
Srinivasan Chakravarthi - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238
H01L 21/336

US Classification:

438231, 438302, 438233

Abstract:

The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). The method comprises growing an oxide layer () on a gate structure () and a substrate () and implanting a dopant () into the substrate () and the oxide layer (). Implantation is such that a portion of the dopant () remains in the oxide layer () to form an implanted oxide layer (). The method further includes depositing a protective oxide layer () on the implanted oxide layer () and forming etch-resistant off-set spacers (). The etch-resistant off-set spacers () are formed adjacent sidewalls of the gate structure () and on the protective oxide layer (). The etch resistant off-set spacers having an inner perimeter () adjacent the sidewalls and an opposing outer perimeter (). The method also comprises removing portions of the protective oxide layer () lying outside the outer perimeter () of the etch-resistant off-set spacers (). Other embodiments of the present invention include a transistor device () and method of manufacturing an integrated circuit ().

US Patent:

20020052083, May 2, 2002

Filed:

Oct 4, 2001

Appl. No.:

09/971198

Inventors:

Xin Zhang - Plano TX, US
Douglas Grider - McKinney TX, US
Jarvis Jacobs - Richardson TX, US
Howard Tigelaar - Allen TX, US

International Classification:

H01L021/8234

US Classification:

438/275000

Abstract:

A method of forming LV and HV transistors with independently optimized threshold adjust (Vt) implants to minimize reverse short channel effects. A through-the-poly implant is used for the Vt implants after gate () formation. The Vt implants for the LV transistors () are performed after the LDD patterns (). The Vt implants for the HV transistors () are performed after the I/O LDD patterns ().

US Patent:

20060001105, Jan 5, 2006

Filed:

Jul 12, 2005

Appl. No.:

11/179210

Inventors:

Brian Hornung - Richardson TX, US
Xin Zhang - Plano TX, US
Lance Robertson - Rockwall TX, US
Srinivasan Chakravarthi - Richardson TX, US
P. Chidambaram - Richardson TX, US

International Classification:

H01L 29/76

US Classification:

257368000

Abstract:

The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). The method comprises growing an oxide layer () on a gate structure () and a substrate () and implanting a dopant () into the substrate () and the oxide layer (). Implantation is such that a portion of the dopant () remains in the oxide layer () to form an implanted oxide layer (). The method further includes depositing a protective oxide layer () on the implanted oxide layer () and forming etch-resistant off-set spacers (). The etch-resistant off-set spacers () are formed adjacent sidewalls of the gate structure () and on the protective oxide layer (). The etch resistant off-set spacers having an inner perimeter () adjacent the sidewalls and an opposing outer perimeter (). The method also comprises removing portions of the protective oxide layer () lying outside the outer perimeter () of the etch-resistant off-set spacers (). Other embodiments of the present invention include a transistor device () and method of manufacturing an integrated circuit ().

US Patent:

20060017079, Jan 26, 2006

Filed:

Jul 21, 2004

Appl. No.:

10/896421

Inventors:

Srinivasan Chakravarthi - Murphy TX, US
Amitabh Jain - Allen TX, US
Xin Zhang - Plano TX, US

International Classification:

H01L 29/76
H01L 21/425
H01L 31/117
H01L 21/44

US Classification:

257288000, 438514000, 438660000, 257616000

Abstract:

We disclose a process for forming ultra shallow np junctions. The junction is formed by, for example, implanting 3E14 ions/cmof antimony ions at 5 keV into silicon. The silicon is pre-amorphized by a previous ion-implantation. The pre-amorphizing implant species may be germanium or arsenic. Germanium may be implanted at 15 keV and Arsenic may be implanted at 2 keV. Both the pre-amorphizing implant and the antimony implant are preferably through bare silicon surface—not covered with any foreign material with the exception of possibly a layer of native oxide. The junction is annealed at about 950 C. following the implants to re-crystallize the implanted region and to activate the implanted ions. The ultra shallow junction is superior because it has a abrupt junction, high sheet resistance and can be formed with low thermal budget.

US Patent:

20130293884, Nov 7, 2013

Filed:

May 1, 2013

Appl. No.:

13/986424

Inventors:

Woonjoo Lee - Daejeon, KR
Seung Yong Lee - North Bethesda MD, US
Oded Rabin - Washington DC, US
Robert M. Briber - Bethesda MD, US
Xin Zhang - College Park MD, US

Assignee:

University of Maryland, College Park - College Park MD

International Classification:

G01N 21/01
G01N 21/65

US Classification:

356301, 428206, 427340

Abstract:

The present invention is directed to self-assembled nanoparticle arrays, methods of making the nanoparticle arrays, and methods of using the nanoparticle arrays in spectroscopic methods for detecting targets of interest. The present invention is also directed to a fabrication method for surface-enhanced Raman scattering (SERS) substrates that possess a unique combination of three highly desirable attributes: (a) the SERS substrates can be tuned to match the laser wavelength of operation and maximize the enhancement factor for the particular Raman instrument and analyte in use; (b) the SERS substrates have a highly reproducible enhancement factor over macroscopic sampling areas; and (c) the fabrication method is achieved without resorting to expensive, slow nano-lithography tools.

US Patent:

61211648, Sep 19, 2000

Filed:

Oct 24, 1997

Appl. No.:

8/957058

Inventors:

Ellie Yieh - Millbrae CA
Xin Zhang - Plano TX
Bang Nguyen - Fremont CA
Stuardo Robles - Sunnyvale CA
Peter Lee - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2131
H01L 21469

US Classification:

438790

Abstract:

A method and apparatus for forming a halogen-doped silicon oxide film, preferably a fluorinated silicon glass (FSG) film, having compressive stress less than about -5. times. 10. sup. 8 dynes/cm. sup. 2. In a specific embodiment, the FSG film is formed by a sub-atmospheric CVD thermal process at a pressure of between about 60-650 torr. The relatively thin film, besides having a low dielectric constant and good gap fill capability, has low compressive stress, and is particularly suitable for use as an intermetal (IMD) layer.

US Patent:

20150301254, Oct 22, 2015

Filed:

Aug 3, 2012

Appl. No.:

13/566452

Inventors:

Grace D. Metcalfe - Bethesda MD, US
Michael Wraback - Germantown MD, US
Andrew Clare Strikwerda - Jamaica Plain MA, US
Richard Douglas Averitt - Newton MA, US
Kebin Fan - Boston MA, US
Xin Zhang - Medford MA, US

Assignee:

U.S. Government as represented by the Secretary of the Army - Adelphi MD

International Classification:

G02B 5/30

Abstract:

A reflection-mode waveplate for operation in the terahertz region by shifting the phase between two perpendicular polarization components of the light wave, comprising a ground plane; an array of polygonal unit cells; the polygonal unit cells comprising a polymer positioned between the ground plane and the exterior of the array of polygonal patches.