Xinhui Wang

US Patent:

7872303, Jan 18, 2011

Filed:

Aug 14, 2008

Appl. No.:

12/191425

Inventors:

Kevin K. Chan - Staten Island NY, US
Qiqing Christine Ouyang - Yorktown Heights NY, US
Xinhui Wang - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

257329, 257332, 257369, 257619, 257E21403, 257E21632, 257E27067, 257E29056, 257E29246, 257E29275

Abstract:

At least one gate dielectric, a gate electrode, and a gate cap dielectric are formed over at least one channel region of at least one semiconductor fin. A gate spacer is formed on the sidewalls of the gate electrode, exposing end portions of the fin on both sides of the gate electrode. The exposed portions of the semiconductor fin are vertically and laterally etched, thereby reducing the height and width of the at least one semiconductor fin in the end portions. Exposed portions of the insulator layer may also be recessed. A lattice-mismatched semiconductor material is grown on the remaining end portions of the at least one semiconductor fin by selective epitaxy with epitaxial registry with the at least one semiconductor fin. The lattice-mismatched material applies longitudinal stress along the channel of the finFET formed on the at least one semiconductor fin.

US Patent:

7955928, Jun 7, 2011

Filed:

Mar 30, 2009

Appl. No.:

12/413836

Inventors:

Kevin K. Chan - Staten Island NY, US
Zhibin Ren - Hopewell Junction NY, US
Xinhui Wang - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8242

US Classification:

438249, 257E21468

Abstract:

A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing.

US Patent:

8431994, Apr 30, 2013

Filed:

Mar 16, 2010

Appl. No.:

12/724555

Inventors:

Kevin K. Chan - Staten Island NY, US
Zhibin Ren - Hopewell Jct. NY, US
Xinhui Wang - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/76

US Classification:

257345, 257410, 257412, 257413, 257E29286

Abstract:

Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.

US Patent:

20110079855, Apr 7, 2011

Filed:

Oct 6, 2009

Appl. No.:

12/574296

Inventors:

Kevin K. CHAN - Staten Island NY, US
Zhibin REN - Hopewell Junction NY, US
Xinhui WANG - Portland OR, US
Keith Kwong Hon WONG - Wappingers Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 27/088
H01L 21/8234
G06F 17/50

US Classification:

257368, 438300, 257E21619, 257E2706, 716136, 716100

Abstract:

FinFETs are merged together by a metal. The method of manufacturing the FinFETs include forming a plurality of fin bodies on a substrate and merging the fin bodies with a metal. The method further includes implanting source and drain regions through the metal.

US Patent:

20130032865, Feb 7, 2013

Filed:

Sep 7, 2012

Appl. No.:

13/606873

Inventors:

Kevin K. Chan - Staten Island NY, US
Young-Hee Kim - Mohegan Lake NY, US
Isaac Lauer - Mahopac NY, US
Ramachandran Muralidhar - Mahopac NY, US
Xinhui Wang - Poughkeepsie NY, US
Min Yang - Yorktown Heights NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78

US Classification:

257288, 257E29255

Abstract:

Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300 C. and 750 C. The dopant layer includes at least 4×10active dopant atoms per cmthat react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

US Patent:

20130032883, Feb 7, 2013

Filed:

Aug 4, 2011

Appl. No.:

13/198255

Inventors:

Kevin K. Chan - Staten Island NY, US
Young-Hee Kim - Mohegan Lake NY, US
Isaac Lauer - Mahopac NY, US
Ramachandran Muralidhar - Mahopac NY, US
Xinhui Wang - Poughkeepsie NY, US
Min Yang - Yorktown Heights NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78
H01L 21/336
H01L 21/24

US Classification:

257365, 438537, 438301, 257408, 257E29264, 257E21409, 257E21154

Abstract:

Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300 C. and 750 C. The dopant layer includes at least 4×10active dopant atoms per cmthat react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

US Patent:

20140070316, Mar 13, 2014

Filed:

Sep 13, 2012

Appl. No.:

13/614062

Inventors:

Kevin K. Chan - Staten Island NY, US
Jinghong Li - Poughquag NY, US
Xinhui Wang - Poughkeepsie NY, US
Yun-Yu Wang - Poughquag NY, US
Qingyun Yang - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L 21/336
H01L 29/78

US Classification:

257347, 438151, 438197, 257E21409, 257E29255

Abstract:

A method of forming a semiconductor structure may include forming at least one fin and forming, over a first portion of the at least one fin structure, a gate. Gate spacers may be formed on the sidewalls of the gate, whereby the forming of the spacers creates recessed regions adjacent the sidewalls of the at least one fin. A first epitaxial region is formed that covers both one of the recessed regions and a second portion of the at least one fin, such that the second portion extends outwardly from one of the gate spacers. A first epitaxial layer is formed within the one of the recessed regions by etching the first epitaxial region and the second portion of the at least one fin. A second epitaxial region is formed at a location adjacent one of the spacers and over the first epitaxial layer within one of the recessed regions.

US Patent:

20200051984, Feb 13, 2020

Filed:

Oct 21, 2019

Appl. No.:

16/658326

Inventors:

- Armonk NY, US
Sivananda K. Kanakasabapathy - Pleasanton CA, US
Babar A. Khan - Ossining NY, US
Masaharu Kobayashi - Tokyo, JP
Effendi Leobandung - Stormville NY, US
Theodorus E. Standaert - Clifton Park NY, US
Xinhui Wang - Poughkeepsie NY, US

International Classification:

H01L 27/108
H01L 29/51
H01L 29/06
G06F 17/50
H01L 27/07
H01L 29/04
H01L 49/02
H01L 27/12
H01L 29/94
H01L 29/66
H01L 21/84

Abstract:

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.