Xinhui Wang from Congers, NY

Us Patents

Method For Fabricating An Ultralow Dielectric Constant Material As An Intralevel Or Interlevel Dielectric In A Semiconductor Device And Electronic Device Made
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US Patent:

7049247, May 23, 2006
Filed:

May 3, 2004
Appl. No.:

10/838849
Inventors:

Stephen M. Gates - Ossining NY, US
Alfred Grill - White Plains NY, US
David R. Medeiros - Ossining NY, US
Deborah Neumayer - Danbury CT, US
Son Van Nguyen - Yorktown Heights NY, US
Vishnubhai V. Patel - Yorktown Heights NY, US
Xinhui Wang - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/31
US Classification:

438778, 438780, 438782
Abstract:

A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

Method For Fabricating An Ultralow Dielectric Constant Material As An Intralevel Or Interlevel Dielectric In A Semiconductor Device And Electronic Device Made
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US Patent:

7312524, Dec 25, 2007
Filed:

Jan 3, 2006
Appl. No.:

11/324479
Inventors:

Stephen M. Gates - Ossining NY, US
Alfred Grill - White Plains NY, US
David R. Medeiros - Ossining NY, US
Deborah Newmayer - Danbury CT, US
Son Van Nguyen - Yorktown Heights NY, US
Vishnubhai V. Patel - Yorktown Heights NY, US
Xinhui Wang - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 23/12
H01L 23/053
US Classification:

257701, 257760, 257E21, 257 17, 257277, 257218
Abstract:

A method for fabricating a thermally stable ultralow dielectric constant film including Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

Ultrathin Soi Cmos Devices Employing Differential Sti Liners
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US Patent:

7659583, Feb 9, 2010
Filed:

Aug 15, 2007
Appl. No.:

11/839272
Inventors:

Zhibin Ren - Hopewell Junction NY, US
Ghavam Shahidi - Pound Ridge NY, US
Dinkar V. Singh - Chicago IL, US
Jeffrey W. Sleight - Ridgefield CT, US
Xinhui Wang - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 27/01
H01L 27/12
H01L 31/0392
US Classification:

257351, 257370, 257378, 438199, 438204
Abstract:

An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.

Process For Making A Mcsfet
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US Patent:

7682913, Mar 23, 2010
Filed:

Jan 26, 2009
Appl. No.:

12/359731
Inventors:

Xu Ouyang - Hopewell Junction NY, US
Louis Lu-Chen Hsu - Fishkill NY, US
Xinhui Wang - Poughkeepsie NY, US
Haizhou Yin - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/336
US Classification:

438289, 257E29264, 257E21135
Abstract:

A process for making a MCSFET includes providing a first implant through a first side of an elongated stack, and then providing a second implant through a second side of the stack. The first implant has a dose different than the dose of the second implant, so that final dopant concentrations in the first and second sides differ and the transistor has two threshold voltages Vt, Vt.

Ultrathin Soi Cmos Devices Employing Differential Sti Liners
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US Patent:

8021956, Sep 20, 2011
Filed:

Jan 6, 2010
Appl. No.:

12/652918
Inventors:

Zhibin Ren - Hopewell Junction NY, US
Ghavam Shahidi - Pound Ridge NY, US
Dinkar V. Singh - Chicago IL, US
Jeffrey W. Sleight - Ridgefield CT, US
Xinhui Wang - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/76
US Classification:

438424, 438199, 438204, 257351, 257370
Abstract:

An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.

Method For Manufacturing A Finfet Device Comprising A Mask To Define A Gate Perimeter And Another Mask To Define Fin Regions
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US Patent:

8202780, Jun 19, 2012
Filed:

Jul 31, 2009
Appl. No.:

12/533389
Inventors:

Zhibin Ren - Hopewell Junction NY, US
Xinhui Wang - Hopewell Junction NY, US
Kevin K. Chan - Hopewell Junction NY, US
Ying Zhang - Yorktown Heights NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/336
US Classification:

438270, 438156, 438212, 438268, 257329, 257E2141
Abstract:

A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.

Semiconductor Devices With Vertical Extensions For Lateral Scaling
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US Patent:

8299546, Oct 30, 2012
Filed:

Mar 25, 2010
Appl. No.:

12/731481
Inventors:

Zhibin Ren - Hopewell Junction NY, US
Kevin K. Chan - Staten Island NY, US
Chung-Hsun Lin - White Plains NY, US
Xinhui Wang - Poughkeepsie NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/86
H01L 21/8238
US Classification:

257408, 257403, 257E21119, 257E29264, 257E2927, 257E29267, 438217, 438221, 438231
Abstract:

A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate.

Self-Aligned Contacts For Field Effect Transistor Devices
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US Patent:

8367508, Feb 5, 2013
Filed:

Apr 9, 2010
Appl. No.:

12/757201
Inventors:

Dechao Guo - Wappingers Falls NY, US
Wilfried E. Haensch - Somers NY, US
Xinhui Wang - Poughkeepsie NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/336
US Classification:

438300, 438149, 438581, 438583, 438587, 438588, 257E21294, 257 59, 257223
Abstract:

A method for forming a field effect transistor includes forming a gate stack, a spacer adjacent to opposing sides of the gate stack, a silicide source region and a silicide drain region on opposing sides of the spacer, epitaxially growing silicon on the source region and the drain region; forming a liner layer on the gate stack and the spacer, removing a portion of the liner layer to expose a portion of the hardmask layer, removing the exposed portions of the hardmask layer to expose a silicon layer of the gate stack, removing exposed silicon to expose a portion of a metal layer of the gate stack, the source region, and the drain region; and depositing a conductive material on the metal layer of the gate stack, the silicide source region, and the silicide drain region.