Yan Ting Li

Address:

PO Box 28206, Oakland, CA 94604

VIN:

4JGBF71E57A292707

Make:

MERCEDES-BENZ

Model:

GL-CLASS

Year:

2007

Address:

PO Box 28206, Oakland, CA 94604

VIN:

4JGBB86EX7A290882

Make:

MERCEDES-BENZ

Model:

M-CLASS

Year:

2007

US Patent:

6754828, Jun 22, 2004

Filed:

Jul 13, 1999

Appl. No.:

09/352715

Inventors:

Suresh Marisetty - San Jose CA
Andrew J. Fish - Olympia WA
Yan Li - Olympia WA
Mani Ayyar - Cupertino CA
Amy ODonnell - Chandler AZ
George Thangadurai - Santa Clara CA
Sham M. Datta - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 942

US Classification:

713200, 713 1, 713 2, 713187, 713201, 710 22, 709310

Abstract:

A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e. g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine.

US Patent:

6771536, Aug 3, 2004

Filed:

Feb 27, 2002

Appl. No.:

10/086495

Inventors:

Yan Li - Milpitas CA
Jian Chen - San Jose CA

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518502, 36518511, 36518518, 36518527, 36518529

Abstract:

The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

US Patent:

6781877, Aug 24, 2004

Filed:

Sep 6, 2002

Appl. No.:

10/237426

Inventors:

Khandker N. Quader - Sunnyvale CA
Yan Li - Milpitas CA
Jian Chen - San Jose CA
Yupin Fong - Fremont CA

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518503, 36518518, 36518528

Abstract:

Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

US Patent:

6859397, Feb 22, 2005

Filed:

Mar 5, 2003

Appl. No.:

10/379608

Inventors:

Jeffrey W. Lutze - San Jose CA, US
Jian Chen - San Jose CA, US
Yan Li - Milpitas CA, US
Masaaki Higashitani - Cupertino CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518528, 36518517, 365196

Abstract:

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e. g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

US Patent:

6870768, Mar 22, 2005

Filed:

Aug 20, 2004

Appl. No.:

10/923320

Inventors:

Khandker N. Quader - Sunnyvale CA, US
Yan Li - Milpitas CA, US
Jian Chen - San Jose CA, US
Yupin Fong - Fremont CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518503, 36518518, 36518522

Abstract:

Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

US Patent:

6914823, Jul 5, 2005

Filed:

Jul 29, 2003

Appl. No.:

10/628962

Inventors:

Jian Chen - San Jose CA, US
Yan Li - Milpitas CA, US
Jeffrey W. Lutze - San Jose CA, US

Assignee:

Sandisk Corporation - Sunnyvale CA

International Classification:

G11C016/06

US Classification:

36518522, 36518502, 36518503, 36518524

Abstract:

In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

US Patent:

6917542, Jul 12, 2005

Filed:

Jul 29, 2003

Appl. No.:

10/629068

Inventors:

Jian Chen - San Jose CA, US
Yan Li - Milpitas CA, US
Jeffrey W. Lutze - San Jose CA, US

Assignee:

Sandisk Corporation - Sunnyvale CA

International Classification:

G11C016/00

US Classification:

36518522, 36518503, 36518533

Abstract:

In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

US Patent:

6975537, Dec 13, 2005

Filed:

Feb 3, 2005

Appl. No.:

11/049802

Inventors:

Jeffrey W. Lutze - San Jose CA, US
Jian Chen - San Jose CA, US
Yan Li - Milpitas CA, US
Masaaki Higashitani - Cupertino CA, US

Assignee:

Sandisk Corporation - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518518, 36518517, 365196

Abstract:

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e. g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.