Yen Hsu Chang

US Patent:

53771222, Dec 27, 1994

Filed:

Nov 1, 1993

Appl. No.:

8/147419

Inventors:

Jeffrey A. Werner - San Jose CA
Daniel R. Watkins - Los Altos CA
Jimmy S. Wong - Cupertino CA
Yen C. Chang - Saratoga CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1560

US Classification:

364488

Abstract:

A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.

US Patent:

54024994, Mar 28, 1995

Filed:

Aug 7, 1992

Appl. No.:

7/927100

Inventors:

Jerel D. Robison - Sunnyvale CA
David D. Miller - Oakland CA
Arthur Scott - Menlo Park CA
Yen C. Chang - Saratoga CA
Edward X. Wang - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04B 100

US Classification:

381119

Abstract:

A multimedia controller apparatus provides for computer programmed volume control and summing of audio signals in an enhanced multimedia environment. The apparatus is capable of receiving and processing inputs from a CD-ROM FM synthesizer, general MIDI audio, microphone, PCM sampled sound, and telephony systems. From these inputs, it produces outputs for PCM sampled sound, telephony systems, and stereo line-out. Additionally, it provides for the integration of telephonic support functions into a multimedia system. The multimedia controller apparatus comprises a volume control portion for receiving and controlling the volume of a plurality of analog input signals. The volume controlled input signals are then combined by an aggregation portion. A telephony processing portion is also provided for processing the telephony input signals. Stereo outputs, mono outputs, digital samplable outputs, and telephony outputs can be formed from the combined analog and telephony signals by an output portion.

US Patent:

51754533, Dec 29, 1992

Filed:

Mar 9, 1992

Appl. No.:

7/847857

Inventors:

Yen C. Chang - Saratoga CA
Jimmy Wong - Cupertino CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 513
H03K 5159

US Classification:

307603

Abstract:

A periodic sequence of signals is intiated and provided to a counter. During this time, a pulse (PULSE) is generated. Upon reaching a terminal count the pulse is terminated. The pulse is provided to a delay element which receives at its input a signal (s) entering, processed within or exiting a semiconductor device. The pulse and periodic sequence of signals are initiated by an edge detector detecting a trigger signal (TRIGGER), which may be the signal (s) being delayed. The sequence of signals is generated by a circuit element, such as a ring oscillator, and the periodicity of the sequence of signals is related to the inherent switching speed of the semiconductor device technology. A plurality of delay circuits are provided in a semiconductor device for individually delaying a plurality of signals entering, processed within and exiting the device. A library of delay circuits may pre-designed, and stored for implementation, as needed, in semiconductor devices.

US Patent:

51558190, Oct 13, 1992

Filed:

Feb 4, 1991

Appl. No.:

7/651111

Inventors:

Daniel Watkins - Saratoga CA
Yen Chang - Saratoga CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 922

US Classification:

395375

Abstract:

A general purpose architecture for a digital microcomputer, which includes a central processing unit, random access memory, user-defined dedicated functions and an optional programmable read only memory. Instructions are fetched either externally or from the optionally ROM. Data can be fetched externally or internally. Each instruction fetched is interpreted by a general-purpose microengine. The architecture is flexible enough to permit the modular addition, deletion and modification of dedicated functions and microinstructions (including changes in execution timing and decoding), as well as the testing of memory independently from the rest of the architecture.

US Patent:

51611198, Nov 3, 1992

Filed:

Feb 14, 1990

Appl. No.:

7/479933

Inventors:

Yen C. Chang - Saratoga CA
Jeffrey A. Werner - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 750

US Classification:

364786

Abstract:

An adder array for adding two or more input addends, whose bit lengths are not necessarily matched, and a method of configuring the adder array are disclosed. The addends are organized according to bit weight, and bits of equal weight are added in adder columns. Carry-outs are introduced into subsequent, higher weight adder columns according to delay. Thereby, the delay associated with the addition of the addends is minimized. Method and apparatus is disclosed.