Ying Li

US Patent:

7306983, Dec 11, 2007

Filed:

Dec 10, 2004

Appl. No.:

10/905024

Inventors:

Dureseti Chidambarrao - Weston CT, US
Ying Li - Newburgh NY, US
Rajeev Malik - Pleasantville NY, US
Shreesh Narasimha - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438199, 438230, 438581, 438583, 438791, 438FOR 431, 257E21292, 257E21293

Abstract:

The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a protective layer to a device, applying a first silicon nitride liner to the device, removing a portion of the first silicon nitride liner, removing a portion of the protective layer, and applying a second silicon nitride liner to the device.

US Patent:

7348635, Mar 25, 2008

Filed:

Dec 10, 2004

Appl. No.:

10/905025

Inventors:

Dureseti Chidambarrao - Weston CT, US
Ying Li - Newburgh NY, US
Rajeev Malik - Pleasantville NY, US
Shreesh Narasimha - Beacon NY, US
Haining Yang - Wappingers Falls NY, US
Huilong Zhu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31/00

US Classification:

257369, 257E27062

Abstract:

The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

US Patent:

7424472, Sep 9, 2008

Filed:

May 27, 2005

Appl. No.:

11/138685

Inventors:

Chuang Wang - Beijing, CN
Joshua Forman - Somerville MA, US
Lee Wang - Kirkland WA, US
Xing Xie - Beijing, CN
Ying Li - Bellevue WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 7/00
G06F 17/30

US Classification:

707 4, 707 3, 715200

Abstract:

A system and method for location-specific searching. The invention correctly identifies explicit and implicit locations in a search query, and provides an appropriate dominant location. Top search results are obtained and analyzed to determine which terms in the query often appear in combination, and the query is tokenized based on the analysis. An explicit location indicating a location intent is most likely treated as an individual token, and the explicit location is treated as the dominant location of the query. In the case of a false positive, wherein the explicit location in a query is not the location intent, the explicit location is likely to be present with other terms that provide context. A token will likely include these terms together. The explicit location will therefore not be used to generate location-specific results in the case of a false positive.

US Patent:

7446062, Nov 4, 2008

Filed:

Dec 10, 2004

Appl. No.:

10/905027

Inventors:

Dureseti Chidambarrao - Weston CT, US
Ying Li - Newburgh NY, US
Rajeev Malik - Pleasantville NY, US
Shreesh Narasimha - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/318
H01L 21/44

US Classification:

438791, 438655, 438682

Abstract:

The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.

US Patent:

7446395, Nov 4, 2008

Filed:

Aug 28, 2007

Appl. No.:

11/845888

Inventors:

Dureseti Chidambarrao - Weston CT, US
Ying Li - Newburgh NY, US
Rajeev Malik - Pleasantville NY, US
Shreesh Narasimha - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/58

US Classification:

257640, 257641, 257649, 257760, 257E21148, 438FOR 127

Abstract:

The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor device comprising a protective layer adjacent a first device, a first silicon nitride liner over the protective layer, a second silicon nitride liner adjacent a second device, and a first silicide layer adjacent the first device and a second silicide layer adjacent the second device, wherein a thickness is substantially the same in the first and second silicide layers.

US Patent:

D592248, May 12, 2009

Filed:

Feb 29, 2008

Appl. No.:

29/304394

Inventors:

Matthew J. Gerules - Chicago IL, US
Ying Li - Vernon Hills IL, US
Steffen F. Koury - Everett MA, US

Assignee:

Parker Pen Products - Great Britain

International Classification:

1906

US Classification:

D19 50

US Patent:

7732270, Jun 8, 2010

Filed:

Jan 11, 2008

Appl. No.:

11/972964

Inventors:

Dureseti Chidambarrao - Weston CT, US
Ying Li - Newburgh NY, US
Rajeev Malik - Pleasantville NY, US
Shreesh Narasimha - Beacon NY, US
Haining Yang - Wappingers Fall NY, US
Huilong Zhu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8238

US Classification:

438199, 438938, 257E27046

Abstract:

The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

US Patent:

7928571, Apr 19, 2011

Filed:

Sep 6, 2007

Appl. No.:

11/850968

Inventors:

Dureseti Chidambarrao - Weston CT, US
Ying Li - Newburgh NY, US
Rajeev Malik - Pleasantville NY, US
Shreesh Narasimha - Beacon NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088
H01L 29/40
H01L 23/48
H01L 23/52
H01L 23/62

US Classification:

257754, 257384, 257768

Abstract:

The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.