Yongmin M Kim

US Patent:

7383426, Jun 3, 2008

Filed:

Jun 11, 2003

Appl. No.:

10/459016

Inventors:

Chris Y. Chung - Houston TX, US
Ravi A. Managuli - Seattle WA, US
Yongmin Kim - Seattle WA, US

Assignee:

University of Washington - Seattle WA

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712220

Abstract:

A deep-pipeline system substantially reduces the overhead of setup delays and pipeline delays by dynamically controlling access of a plurality of configuration register sets by both a host central processing unit (CPU) and the stages of the pipelines. A master configuration register set is loaded with configuration parameters by the host CPU in response to an index count provided by a setup-index counter. A plurality of other counters are employed to track timing events in the system. In one embodiment, a run-index counter provides a run-index count to the first stage of the pipeline that is propagated along the stages, enabling configuration register sets to transfer configuration parameters to the stages of the pipeline when required to enable processing of a task. In an alternative embodiment, a plurality of D flip-flops sequentially propagates a state for successive registers, so that the setup-index counter is not required.