Young Min Ko

US Patent:

7471548, Dec 30, 2008

Filed:

Dec 15, 2006

Appl. No.:

11/611569

Inventors:

Christopher V. Baiocco - Newburgh NY, US
Xiangdong Chen - Poughquag NY, US
Young G. Ko - Fishkill NY, US
Melanie J. Sherony - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY
Samsung Electronics Co., Ltd. - Gyeonggi-Do

International Classification:

G11C 11/412
H01L 29/78

US Classification:

365156, 365154, 365 51, 365 72, 257418, 257903

Abstract:

An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

US Patent:

20090166757, Jul 2, 2009

Filed:

Dec 27, 2007

Appl. No.:

11/964879

Inventors:

Christopher V. Baiocco - Newburgh NY, US
Xiandong Chen - Poughquag NY, US
Young G. Ko - Fishkill NY, US
Melanie J. Sherony - Fishkill NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
SAMSUNG ELECTRONICS CO., LTD. - Gyeonggi-Do

International Classification:

G06F 17/50
H01L 27/11

US Classification:

257393, 716 5, 257E27099

Abstract:

A design structure embodied in a machine readable medium is provided for use in the design, manufacturing, and/or testing of Ics that include at least one SRAM cell. In particular, the present invention provides a design structure of an IC embodied in a machine readable medium, the IC including at least one SRAM cell with a gamma ratio of about 1 or greater. In the present invention, the gamma ratio is increased with degraded pFET device performance. Moreover, in the inventive IC, there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides a design structure of an IC embodied in a machine readable medium, the IC comprising at least one static random access memory cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the at least one nFET and the at least one pFET.