Yuan Xiu Li

US Patent:

6351581, Feb 26, 2002

Filed:

Mar 17, 1998

Appl. No.:

09/040477

Inventors:

Christopher Richard Doerr - Middletown NJ
Yuan P. Li - Duluth GA

Assignee:

Agere Systems Optoelectronics Guardian Corp. - Orlando FL

International Classification:

G02B 626

US Classification:

385 24, 359124

Abstract:

An optical add-drop multiplexer (ADM) avoids waveguide crossings by being constructed in the form of a Mach-Zehnder interferometer having a demultiplexer/multiplexer (demux/mux) pair in each of its arms. Each demux/mux pair is interconnected by coherent connecting paths having heating elements for increasing the path length of selected connecting paths. Waveguide optical couplers having asymmetric transfer functions are used at the input and output of the ADM. These couplers cooperate with the activated heating elements to add and/or delete a selected optical channel to/from an optical transmission path. Each coherent connecting path includes a number of waveguides. The end-to-end transmission characteristic of the ADM through each individual waveguide has a Gaussian shape. These Gaussian shapes are designed intersect at their -3 dB wavelengths so that the end-to-end transmission characteristic of the ADM is flat.

US Patent:

20210066177, Mar 4, 2021

Filed:

Nov 11, 2020

Appl. No.:

16/949695

Inventors:

- San Diego CA, US
Yuan LI - Irvine CA, US
Shrestha GANGULY - Bangalore, IN
Terence CHEUNG - San Diego CA, US
Hui WANG - San Diego CA, US

International Classification:

H01L 23/498
H01L 23/538
H01L 25/18
H01L 23/00
H01L 21/48
H01L 25/00

Abstract:

A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

US Patent:

20200211943, Jul 2, 2020

Filed:

Jun 26, 2019

Appl. No.:

16/453803

Inventors:

- San Diego CA, US
Yuan LI - Irvine CA, US
Shrestha GANGULY - Bangalore, IN
Terence CHEUNG - San Diego CA, US
Hui WANG - San Diego CA, US

International Classification:

H01L 23/498
H01L 23/538
H01L 25/18
H01L 23/00
H01L 21/48
H01L 25/00

Abstract:

A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.