Yuan Li

US Patent:

8198699, Jun 12, 2012

Filed:

Apr 19, 2010

Appl. No.:

12/762958

Inventors:

Yuanlin Xie - Fremont CA, US
Yuan Li - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 21/70

US Classification:

257499, 257E2117, 257E2302

Abstract:

Provided is an IC package. In one implementation, the IC package includes a metal pad having a first metal pad surface and a second metal pad surface substantially parallel to the first metal pad surface; a first dielectric layer having a first surface, a second surface, and a third surface, where the first dielectric layer covers a first end portion of the second metal pad surface, and the third surface of the first dielectric layer is substantially parallel to the first and second surfaces of the first dielectric layer; a second dielectric layer having a first surface, a second surface, and a third surface, where the second dielectric layer covers a second end portion of the second metal pad surface, and the third surface of the second dielectric layer is substantially parallel to the first and second surfaces of the second dielectric layer; and a metal structure covering a middle portion of the second metal pad surface, a first end portion of the third surface of the first dielectric layer, and a first end portion of the third surface of the second dielectric layer.

US Patent:

20030190618, Oct 9, 2003

Filed:

Mar 6, 2002

Appl. No.:

10/092885

Inventors:

Babru Samal - N. Potomac MD, US
Yuan Li - Rockville MD, US
Leandro Hermida - Germantown MD, US
Nancy Hoppa - Westminster MD, US
Karl Johe - Potomac MD, US

International Classification:

C12Q001/68
C12P019/34

US Classification:

435/006000, 435/091200

Abstract:

A method for generating five prime biased tandem tag libraries of cDNAs is revealed. The method allows generation of partial sequences consisting of a minimal length of expressed cDNA sequences of at least 20 bases from biological samples to rapidly identify novel expressed transcripts.

US Patent:

20230037380, Feb 9, 2023

Filed:

Oct 21, 2022

Appl. No.:

17/971087

Inventors:

- Mountain View CA, US
Madhusudan K. Iyengar - Foster City CA, US
Connor Burgess - Alameda CA, US
Padam Jain - San Jose CA, US
Yuan Li - Sunnyvale CA, US
Feini Zhang - Fremont CA, US

International Classification:

H01L 23/433
H01L 25/065

Abstract:

Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.

US Patent:

20210366806, Nov 25, 2021

Filed:

May 20, 2020

Appl. No.:

16/879101

Inventors:

- Mountain View CA, US
Connor Burgess - Alameda CA, US
Padam Jain - San Jose CA, US
Jorge Padilla - Union City CA, US
Feini Zhang - Sunnyvale CA, US
Yuan Li - Sunnyvale CA, US

International Classification:

H01L 23/433
F28F 9/02
H05K 7/20

Abstract:

Systems and methods for using spring force based compliance to minimize the bypass liquid flow gaps between the tops of chip microfins and bottom side of manifold ports are disclosed herein. A fluid delivery and exhaust manifold structure provides direct liquid cooling of a module. The manifold sits on top of a chip with flow channels. Inlet and outlet channels of the manifold in contact with flow channels of the chip creates an intricate crossflow path for the coolant resulting in improved heat transfer between the chip and the working fluid. The module is also designed with pressure reduction features using internal leakage flow openings to account for pressure differential between fluid entering and being expelled from the module.

US Patent:

20210366807, Nov 25, 2021

Filed:

May 21, 2020

Appl. No.:

16/880417

Inventors:

- Mountain View CA, US
Madhusudan K. Iyengar - Foster City CA, US
Connor Burgess - Alameda CA, US
Padam Jain - San Jose CA, US
Yuan Li - Sunnyvale CA, US
Feini Zhang - Sunnyvale CA, US

International Classification:

H01L 23/433
H01L 25/065

Abstract:

Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.

US Patent:

20210366841, Nov 25, 2021

Filed:

May 19, 2020

Appl. No.:

16/877730

Inventors:

- Mountain View CA, US
Connor Burgess - Alameda CA, US
Padam Jain - San Jose CA, US
Yuan Li - Sunnyvale CA, US

International Classification:

H01L 23/00
H01L 23/16
H01L 23/473

Abstract:

A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

US Patent:

20200090039, Mar 19, 2020

Filed:

Nov 17, 2017

Appl. No.:

16/494842

Inventors:

- Mountain View CA, US
Yuan Li - Fremont CA, US
Bo Wu - Pleasanton CA, US
Chao-Yeh Chen - Mountain View CA, US
Xiao Zhang - Mountain View CA, US
Hartwig Adam - Marina del Rey CA, US

International Classification:

G06N 3/08
G06N 20/00
G06K 9/32

Abstract:

A computer-implemented method for generating a unified machine learning model using a neural network on a data processing apparatus is described. The method includes the data processing apparatus determining respective learning targets for each of a plurality of object verticals. The data processing apparatus determines the respective learning targets based on two or more embedding outputs of the neural network. The method also includes the data processing apparatus training the neural network to identify data associated with each of the plurality of object verticals. The data processing apparatus trains the neural network using the respective learning targets and based on a first loss function. The data processing apparatus uses the neural network trained to generate a unified machine learning model, where the model is configured to identify particular data items associated with each of the plurality of object verticals.