Yuan Xian Lu

US Patent:

7973418, Jul 5, 2011

Filed:

Apr 21, 2008

Appl. No.:

12/107009

Inventors:

Reynante Alvarado - Chandler AZ, US
Yuan Lu - Phoenix AZ, US
Richard Redburn - Phoenix AZ, US

Assignee:

Flipchip International, LLC - Phoenix AZ

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257780, 257E23021

Abstract:

An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0. 5:1 to 0. 95:1. Also, the shortest distance from the center of the polymer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0. 35:1 to 0. 85:1. Additionally, the shortest distance from the center of the passivation layer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0. 35:1 to 0. 80:1.

US Patent:

8143722, Mar 27, 2012

Filed:

Oct 4, 2007

Appl. No.:

11/867646

Inventors:

Anthony Curtis - Gilbert AZ, US
Guy F. Burgess - Gilbert AZ, US
Michael Johnson - Tempe AZ, US
Ted Tessier - Chandler AZ, US
Yuan Lu - Phoenix AZ, US

Assignee:

Flipchip International, LLC - Phoenix AZ

International Classification:

H01L 23/48
H01L 23/52

US Classification:

257738, 257772, 257778

Abstract:

An interconnect structure comprises a solder including nickel (Ni) and tin (Sn), with the nickel in a range of 0. 01 to 0. 20 percent by weight. The interconnect structure further includes an intermetallic compound (IMC) layer in contact with the solder. The (IMC) layer comprises a compound of copper and nickel.

US Patent:

8188606, May 29, 2012

Filed:

Apr 13, 2011

Appl. No.:

13/085759

Inventors:

Reynante Alvarado - Chandler AZ, US
Yuan Lu - Phoenix AZ, US
Richard Redburn - Phoenix AZ, US

Assignee:

Flipchip International, LLC - Phoenix AZ

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257780, 257E23021

Abstract:

A semiconductor package includes a device pad on a substrate. A polybenzoxazole (PBO) layer overlies the substrate, and the PBO layer has an opening to expose the device pad. A redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the PBO layer and conductively coupled to the device pad. A polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the polymer layer. The UBM electrically connects to the landing pad through an opening in the polymer layer. A solder bump is secured to the UBM. A shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0. 5:1 up to 0. 95:1.

US Patent:

8446019, May 21, 2013

Filed:

Apr 26, 2012

Appl. No.:

13/457311

Inventors:

Reynante Alvarado - Chandler AZ, US
Yuan Lu - Phoenix AZ, US
Richard Redburn - Phoenix AZ, US

Assignee:

Flipchip International, LLC - Phoenix AZ

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257780, 257E23021

Abstract:

A semiconductor package includes a device pad on a substrate. A first polymer layer overlies the substrate, and the first polymer layer has an opening to expose the device pad. In one embodiment, a redistribution layer (RDL) comprises a landing pad, and the RDL is positioned on the first polymer layer and conductively coupled to the device pad. A second polymer layer is on the RDL, and an under bump metal pad (UBM) is on the landing pad and extends onto a top surface of the second polymer layer. In one embodiment, a shortest distance from a center of the landing pad to an outer edge of the landing pad, and a shortest distance from a center of the UBM to an outer edge of the UBM are in a ratio that ranges from 0. 5:1 up to 0. 95:1.

US Patent:

20090014869, Jan 15, 2009

Filed:

Oct 28, 2005

Appl. No.:

11/718192

Inventors:

Joan K. Vrtis - Mesa AZ, US
Anthony Curtis - Gilbert AZ, US
Bret Trimmer - Mesa AZ, US
Brian King - Gilbert AZ, US
Yuan Lu - Phoenix AZ, US
Haluk Balkan - Phoenix AZ, US

International Classification:

H01L 23/488
H01L 21/44

US Classification:

257737, 438613, 257E21476, 257E23023

Abstract:

A semiconductor device package, for example a flip-chip package, having a solder bump mounted above a polymer layer for use in flip-chip mounting of a semiconductor device to a circuit board. A polymer layer such as polybenzoxazole is formed overlying a wafer passivation layer. Solder bumps are attached to an under-bump metallization layer and electrically coupled to conductive bond pads exposed by openings in the wafer passivation layer.

US Patent:

20120146219, Jun 14, 2012

Filed:

Feb 16, 2012

Appl. No.:

13/397876

Inventors:

Anthony Curtis - Gilbert AZ, US
Guy F. Burgess - Gilbert AZ, US
Michael Johnson - Tempe AZ, US
Ted Tessier - Chandler AZ, US
Yuan Lu - Phoenix AZ, US

Assignee:

FLIPCHIP INTERNATIONAL, LLC - Phoenix AZ

International Classification:

H01L 23/48

US Classification:

257738, 257778, 257E23021

Abstract:

An interconnect structure comprises a solder including nickel (Ni) in a range of 0.01 to 0.20 percent by weight. The interconnect structure further includes an intermetallic compound (IMC) layer in contact with the solder. The IMC layer comprises a compound of copper and nickel.