Yuan X Lu

US Patent:

6389374, May 14, 2002

Filed:

Nov 5, 1998

Appl. No.:

09/187055

Inventors:

Jawahar Jain - Santa Clara CA
Yuan Lu - Pittsburgh PA

Assignee:

Fujitsu Limited - Kawasaki

International Classification:

G06F 1710

US Classification:

703 2, 716 3, 716 7

Abstract:

A system and method for determining variable orders for decision diagrams. The variable orders are determined by sampling subspaces of a Boolean space representing a function or circuit. The subspaces are formed in a variety of ways, including through the use of abstraction, decomposition, partial assignments, and circuit subspaces.

US Patent:

7562322, Jul 14, 2009

Filed:

Apr 16, 2007

Appl. No.:

11/735808

Inventors:

Yuan Lu - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 1, 716 2, 716 3, 716 5, 716 18, 703 13, 703 14

Abstract:

Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.

US Patent:

7926020, Apr 12, 2011

Filed:

Feb 8, 2007

Appl. No.:

11/672919

Inventors:

Yuan Lu - San Jose CA, US
Yunshan Zhu - Cupertino CA, US

International Classification:

G06F 17/50

US Classification:

716136

Abstract:

One embodiment of the present invention provides a method that automatically generates assertions of a hardware design. The method includes accessing a trace and a set of predicates of the hardware design. Then, the trace is projected over the set of predicates to generate a second trace. Then, a new set of states of the second trace is computed and the result is represented as a logical formula. The formula is reduced by logic optimization techniques. And finally, a set of logical consequences of the logic formula is produced and each logical consequence is enumerated as an assertion.

US Patent:

8326778, Dec 4, 2012

Filed:

Dec 29, 2009

Appl. No.:

12/649144

Inventors:

Yuan Lu - San Jose CA, US
Yunshan Zhu - Cupertino CA, US

Assignee:

NextOp Software, Inc. - San Jose CA

International Classification:

G06N 5/00

US Classification:

706 12, 706 45

Abstract:

Systems and methods for deriving a predicate by constructing a logic formula from information recorded during test execution, optimizing the logic formula and computing the logical implication of the optimized logic formula. Systems and methods for deriving an assertion from a logical implication by substituting each predicate in the logical implication with corresponding design elements from a hardware design description, inserting the design elements into a target template, inserting a context-sensitive input of the target template based on design elements in the hardware design description and creating an instance name for an instantiation of the target template. Systems and methods for generating a set of clauses that are implied by a disjunctive normal formula of a set of cubes.

US Patent:

8624673, Jan 7, 2014

Filed:

Jan 11, 2012

Appl. No.:

13/348397

Inventors:

Jinho Park - San Jose CA, US
Yuan Lu - Sunnyvale CA, US
Li Lin - Saratoga CA, US

Assignee:

Marvell World Trade Ltd. - Hamilton

International Classification:

H03F 3/26

US Classification:

330267, 330264

Abstract:

The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit.

US Patent:

20050114809, May 26, 2005

Filed:

Apr 29, 2004

Appl. No.:

10/835561

Inventors:

Yuan Lu - San Jose CA, US

International Classification:

G06F009/45
G06F017/50

US Classification:

716005000, 716002000

Abstract:

Formal techniques are applied to industrial design problems such as verification of a circuit design. Initial decisions may include defining properties to verify the design. An abstraction of the design may be generated and model checking applied to the abstraction. Results obtained using these techniques may be extended by performance analysis and/or verification of sequential operations.

US Patent:

20070104187, May 10, 2007

Filed:

Nov 6, 2006

Appl. No.:

11/593103

Inventors:

Vamsi Tatapudi - Santa Clara CA, US
Chien-Hsien Wu - Cupertino CA, US
Yuan Lu - San Jose CA, US

International Classification:

G06F 9/34
H04L 12/50
H04Q 11/00
H04L 12/56

US Classification:

370368000, 370371000, 370374000, 370378000, 370381000, 370412000, 711200000

Abstract:

A method and apparatus for managing memory according to several embodiments of the invention. According to embodiments, the invention includes providing a memory including a plurality of memory locations configured to store data, providing a memory address pool having a plurality of available memory addresses and providing a cell free address pool (CFAP), including a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool.

US Patent:

20100088257, Apr 8, 2010

Filed:

Dec 9, 2009

Appl. No.:

12/634586

Inventors:

Yuan Lu - San Jose CA, US
Yunshan Zhu - Cupertino CA, US

International Classification:

G06F 15/18
G06N 5/02

US Classification:

706 12, 706 56

Abstract:

Systems and methods for deriving a predicate by constructing a logic formula from information recorded during test execution, optimizing the logic formula and computing the logical implication of the optimized logic formula. Systems and methods for deriving an assertion from a logical implication by substituting each predicate in the logical implication with corresponding design elements from a hardware design description, inserting the design elements into a target template, inserting a context-sensitive input of the target template based on design elements in the hardware design description and creating an instance name for an instantiation of the target template. Systems and methods for generating a set of clauses that are implied by a disjunctive normal formula of a set of cubes.